EE 6801

Digital Circuit Design

Lecture 6
Date: 24/11/2020, 03:30 PM
Dr. Md. Selim Hossain
Associate Professor
Office: EEE-305, EEE Building, KUET
Email: selim@eee.kuet.ac.bd
Contact: +8801758688829
Dept. of Electrical and Electronic Engineering (EEE)
Khulna University of Engineering & Technology (KUET)
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 Learning Outcomes (3)
3. Introduction to VLSI Systems Design
• Digital System Design
• VLSI Design Flow
• Introduction to VHDL, VHDL Vs Verilog HDL
• VHDL Learning & how to write a VHDL code for digital Circuit
• Xilinx or Altera FPGA and how to program and operate FPGA Board

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VHDL D Flip-Flop Example with Enable Signal

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VHDL D Flip-Flop Example with Enable Signal

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VHDL Data Objects (Classes)

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VHDL Signal vs variables

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Signal vs variables—timing of signals

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Signal vs variables—timing of variables

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VHDL Concurrent Statements- when else

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VHDL Concurrent Statements- when else…Continue

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VHDL Concurrent Statements—with select: Example 1

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VHDL Concurrent Statements—with select: Example 1

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VHDL Concurrent Statements—with select: Example 2

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VHDL Concurrent Statements—with select: Example 3

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VHDL Concurrent Statements—with select: Example 3

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VHDL Concurrent Statements—component instantiation

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VHDL Concurrent Statements—for generate

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VHDL Concurrent Statements—for generate (an example)

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VHDL Sequential Statements

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VHDL Sequential Statements—if then else

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VHDL Sequential Statements—wait

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VHDL Sequential Statements—case-when

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VHDL Sequential Statements—case-when (null)

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 Any
Questions?

Thank You
Acknowledgement: 1) Dr. Yinan Kong, Senior Lecturer, Macquarie University
2) Wikipedia and some other online materials
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