Introduction to

VLSI Design
 Objectives
The purpose of this lecture is to:
❑Define CMOS VLSI Design
❑Explain the behavior of CMOS transistors as digital
switches
❑Design logic gates using transistors
❑Explain Stick diagrams
❑Create schematic and layout of Inverter using electric
binary software

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 VLSI
❑ Very-large-scale integration (VLSI) is the process of
creating an integrated circuit (IC) by combining
millions of transistors into a single chip.

❑ Before the introduction of VLSI technology, most ICs

had a limited set of functions they could perform.

❑ The electronics industry has achieved a phenomenal

growth over the last few decades, mainly due to the
rapid advances in large scale integration technologies
and system design applications.

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 Transistor Types
❑ Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
❑ Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

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 nMOS Transistor
❑ Four terminals: gate, source, drain, body
❑ Symbol shows gate, source, drain
– Usually omits body
– Source and drain are logically indistinguishable

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 nMOS Transistor
❑ Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– Body is lightly doped p-type
– Gate is metal or polycrystalline silicon (polysilicon)
– SiO2 (oxide) is an excellent insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
❑ Source and drain are
heavily doped (n+) silicon

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 nMOS Operation
❑ Body is usually tied to ground (0 V)
❑ When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF

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 nMOS Operation Cont.
❑ When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

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 pMOS Transistor
❑ Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior

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 Complementary CMOS
❑ Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
❑ Fast, cheap, low power transistors

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

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Transistors as Switches
❑ We can view MOS transistors as electrically
controlled switches
❑ Voltage at gate controls path from source to drain

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 CMOS Inverter

A Y
0 1
1 0 OFF
ON
0
1

ON
OFF

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 CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
0
1 0 1 ON
OFF
1 1 0 0
1
1
0 OFF
ON
ON
OFF

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 Stick Diagrams
❑ Stick diagram is a simple drawing commonly used to
represent layouts.
❑ It shows all layout layers (metals, vias, polies, etc..),
but it does not show the exact placements,
transistors’ sizes, metal lengths, metal widths and
so.
❑ It helps you to plan your layout design quickly.
❑ It is recommended to draw with different colors so
that you can recognize the layers.

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 Stick Diagrams
– Need not be to scale
– Draw with color pencils or dry-erase markers

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 Stick Diagrams
Steps:
1. Understand the schematic of the stick.
2. Detect how many transistors you have, their
sizes and which ones can be shared together.
3. Draw the stick with the shortest path for both
PMOS and NMOS.
4. Make sure your stick is logical and can be
implemented in layout.

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 Stick Diagrams
Conventions:
• A cross between a poly and a diffusion
represents a transistor, as shown below:

• When two or more lines of the same type cross/touch each

other, an electrical contact is represented, as shown below:

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 Stick Diagrams
• When two or more lines of different types
cross/touch each other, no electrical contact is
represented, unless we add a contact or a via, as
shown below:

There is no electrical contact.

There is an electrical contact.

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 Stick Diagrams
Choose the shortest path:

1.It is the path that allows to share as many transistors as

possible with the least number of breaks.

1.It is achieved by sharing diffusions of transistors that have

the same connections on their sources/drains.
For example, if a transistor has a VDD/VSS connection on
its source, then it can be shared with a different transistor
which also has a VDD/VSS connection on its source.

1.Only take source/drain connections as a part of the path.

Never take an input connection (connection on gate).

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Stick Diagrams

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 Stick Diagrams
Examples
NAND Gate.
:

NAND2

B A

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 Stick Diagrams
• D-latch.

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Stick Diagrams

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 Layout
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Express rules in terms of λ = f/2
– E.g. λ = 0.3 μm in 0.6 μm process

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Simplified Design Rules

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 Gate Layout
❑ Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
❑ Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top

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Example: Inverter

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 Example: NAND3
❑ Horizontal N-diffusion and p-diffusion strips
❑ Vertical polysilicon gates
❑ Metal1 VDD rail at top
❑ Metal1 GND rail at bottom

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