VLSI DESIGN (1 MARK QUESTIONS)

1. Define Threshold voltage

Ans: The minimum gate voltage required to create a channel between source and drain is
defined as threshold voltage. (or) gate voltage at which significant current starts to flow from
the source to the drain is defined as threshold voltage.
2. Define operating regions of MOSFET
Ans: Cutoff region, linear region, and saturation region
3. What are the voltage conditions for linear and saturation region
Ans: Vgs≥Vt and Vds<Vgs-Vt (Linear) and Vgs≥Vt and Vds≥Vgs-Vt (Saturation)
4. Define pinch off voltage
Ans: The voltage at which mos transistor enters in saturation region is called pinch off or over
drive voltage.
5. State the Moore’s law
Ans: Moore's law is a term used to refer to the observation made by Gordon Moore in 1965
that the number of transistors in a dense integrated circuit (IC) doubles about every two years.
6. Define photolithography process
Ans: Photolithography is a patterning process in which a photosensitive polymer is selectively
exposed to light through a mask, leaving a latent image in the polymer that can then be
selectively dissolved to provide patterned access to an underlying substrate.
7. Difference between enhancement mode mosfet and depletion mode mosfet
Ans: channel is absent in enhancement mode at vgs=0V and and channel is present in depletion
mode at vgs=0V.
8. List the different aspects of the threshold voltage
Ans: Threshold voltage can be given as

QB: Charge per unit area in the depletion region

Qss: Charge density at Si:Sio2 interface
Co: Capacitance per unit gate area
ϕms: Work function difference between gate and Si
ϕfN: Fermi potential
9. Difference between pull up and pull down network
Ans: The network present between Vdd and Vout is pull-up and The network present between
Vout and ground is pull-down network.
10. Define transconductance (gm) and output conductance (gds)
Ans: The change in Id with the change in Vgs is known as transconductance. The change in Id
with the change in Vds is known as output conductance.
11. Expression for drain current in linear and saturation region
Ans:
12. Why nmos is connected as pull-down and pmos as pull-up in cmos
13. Ans: NMOS gives strong ‘0’ and PMOS gives Strong ‘1’, so nmos is connected as pull-down and
pmos as pull-up in cmos.
14. List the different fabrication process of cmos
Ans: N-well process, P-well process, Twin tub process
15. Draw the circuit for cmos inverter
Ans:

16. Draw the NMOS inverter circuit

Ans:

17. State the different MOS layers used in the fabrication process
Ans: n-diffusion, p-diffusion, polysilicon, and metal
18. Define latch-up in mos circuits
Ans: A latch-up is a type of short circuit which can occur in an integrated circuit. More
specifically it is the creation of a low-impedance short circuit path between the power supply
rails of a MOSFET circuit
19. Draw the Id versus Vds characteristics
Ans:
20. Define figure of merit
Ans: It is the ratio of transconductance to the gate capacitance.

21. Define pass transistor

Ans: A transistor used as a switch to pass logic levels between nodes of a circuit.
22. Draw the transfer characteristics of NMOS inverter
Ans:

23. How to avoid latch-up in CMOS circuits

Ans: (i) Twin tub process (ii) an increase in substrate doping levels with a consequent drop in the
value of Rs (iii Guard rings
24. Difference between contact cut and via cut
Ans: The connection between two different mos layers (poly to metal1 or diffusion to metal1) is
known as contact cut and the connection between metal1 and metal2 is known as via cut.
25. How NMOS and PMOS transistors are represented in stick diagram
Ans:

26. Define stick diagram

Ans: Stick diagrams convey layer information through colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.
27. Difference between λ and μ based design rules.
Ans:

28. Mention the minimum λ based design rules for transistors

Ans:
29. Difference between buried contact and butting contact
Ans:
The gate and source of a depletion device can be connected by a method known as butting
contact. The buried contact is a method to make direct ohmic contact between the polysilicon
gate material and the junctions, in silicon-gate integrated circuits.
30. Mention the double metal λ based design rules
Ans:
Metal1-3 λ, Metal2-4 λ, Metal1-Metal1 spacing 3 λ, and Metal2-Meta2 spacing 4 λ,
31. Draw the stick diagram for NMOS inverter
Ans:

32. Draw the stick diagram for CMOS inverter

Ans:

33. Draw the stick diagram for NAND gate

Ans:

34. What are the advantages of CMOS logic over bipolar logic
Ans: Low power dissipation, High packing density, High input impedance
35. Define sheet resistance
Ans: Sheet resistance (also known as surface resistance or surface resistivity) is a common
electrical property used to characterize thin films of conducting and semiconducting materials.
36. Calculate the total on resistance of NMOS inverter with Zpu/Zpd=4.
Ans: For pull up 40k and for pull down 10k and the total resistance=50k
37. Define standard unit of capacitance □Cg
Ans: The gate capacitance of a minimum sized transistor (L=W=2λ).
38. Write the standard unit of capacitance □Cg value for 5μm and 2μm technology
Ans: 4x10-4 pF/ μm2 and 8x10-4 pF/ μm2
39. Define delay unit (Ƭ)
Ans:

40. What is the delay of NMOS inverter and NMOS inverter pair.
41. Ans:
Depending on the input signal applied NMOS inverter delay is 1T (or) 4T and NMOS inverter
pair is 5T.
42. What is the delay of CMOS inverter and CMOS inverter pair
Depending on the input signal applied CMOS inverter delay is 2T (or) 5T and CMOS inverter pair
is 7T.
43. List the different circuits used for driving large capacitive loads
Ans: Cascaded inverters as drivers, Super buffers, Bicmos drivers
44. Difference between inverting and non-inverting super buffer
Ans in inverting super buffers Vout is complement of Vin, where as in non inverting super buffer
Vout=Vin.
45. Mention the drawback of long polysilicon wires
Ans: On the layout long polysilicon wires will consume more area and delay.
46. Define fringing field capacitance
Ans: The capacitance exists between two long interconnection metal lines is known as fringing
field capacitance.
47. Define interlayer capacitance.
Ans: The capacitance present between n-diffusion and n-well and p-diffusion and p-well.
48. Importance of scaling in MOS circuits.
Ans: Scaling will reduce transistor feature size and improve packing density.
49. Difference between switch logic and gate logic.
Ans: Switch logic is based on pass transistors or transmission gates. This logic reduces the count
of transistors used to make different logic gates, by eliminating redundant transistors. Gate logic
implemented using pull-up and pull-down networks (cmos logic, nmos logic, and Bicmos logic ).
50. Mention the architectural issues in MOS sub system circuit design
Ans:
i. Define the requirements (properly and carefully).
ii. Partition the overall architecture into appropriate subsystems.
iii. Consider communication paths carefully in order to develop sensible interrelationships
between subsystems.
iv. Draw a floor plan of how the system is to map onto the silicon.
v. Draw suitable stick diagram.
vi. Convert each cell to a layout.
vii. Carefully and thoroughly carry out ' a design rule check on each cell.
viii. Simulate the performance of each cell/subsystem.
51. How transmission gate is formed.
Ans: Parallel combination of nmos and pmos is transmission gate, which can pass signals from
source to drain.
52. Advantage of transmission gate over pass transistor
Ans: Pass transistor will not provide strong’0’ or strong ‘1’, where as transmission gate gives
proper logic levels at the output.
53. Draw the BICMOS inverter circuit
Ans:

54. Mention the difference between even parity and odd parity
Ans: In case of even parity, If number of 1s is even, parity bit value is 0. If number of 1s is odd,
parity bit value is 1. In case of odd parity, If number of 1s is odd, parity bit value is 0. If number
of 1s is even, parity bit value is 1.
55. Rise time and fall time expression for CMOS inverter
Ans:

56. Advantage of CMOS logic over NMOS logic

Ans: CMOS produce proper output logic levels and low power dissipation.
57. List the two scaling factors used in scaling models
Ans: 1/α, 1/β are the two scaling factors used in scaling models.
58. What is demarcation line.
Ans: The line which separates pull-up and pull-down network.
59. Explain pinch-off
Ans: The voltage at which transistor enters into saturation region is known as pinch-off.
60. What is twin-tub process in CMOS.
Ans: Two separate wells are used for fabrication of nmos and pmos transistors.