ECE 5545: Advanced VLSI

Lecture 2: Si CMOS Basics

Dr. Paul K. Ampadu, Ph.D.

ARI/MICS
1
 Announcements
Assignment 0 (5pts): VLSI Inside?
Due Today Canvas W 1/24/24 11:59PM

- Pick Device
- What Chips? What Function? What/How Optimize?

 Last Time
 Introductions & Course Logistics
 Syllabus in Lectures 0 & 1

 1st Reading Assignment: Power TBA, Groups

 Today: Si CMOS Basics, ETC. 2
 Si CMOS Basics
 Brief History
 Gigascale Integration Trends
 Coping with Complexity (Towards 1-T transistors?)
 Silicon Semiconductor Properties (very brief)
 Why CMOS?
 Miniaturization/Scaling & Moore’s Law
 How long can we scale?
 Non Von Neumann Architectures???
 Compute in Memory? Approximate Storage? 3
HW 1 (10-pts): Semiconductor History
 Assignment 2, Due M 1/29/24 (Canvas 11:59PM)
 Vacuum Tubes –1st half of 20th century
 Large, expensive, power-hungry, unreliable
 1947: First point contact transistor by John Bardeen
& Walter Brattain at Bell Labs
 1949: Bipolar Transistor – W. Shockley
 1958/59: First Monolithic IC (2T) – Jack Kilby TI
 1960: 1st commercial IC – Fairchild (Intel folks)
 1962-1990s: TTL
 1974-1980s: ECL
4
 Transistor Revolution
 By 2003
 Intel Pentium-4 µProcessor (55M transistors)
 Cf. 4004 2300 transistors
 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth for 45 yrs
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
5
 Transistor Types
 Bipolar transistors
 NPN or PNP silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density
 Metal Oxide Semiconductor (MOS) FETs
 NMOS and PMOS MOSFETS
 Voltage applied to insulated gate controls current
between source and drain
 Low power allows very high integration 6
 MOSFET Technology
 MOSFET - Lilienfeld (Canada) in 1925 and Heil
(England) in 1935
 CMOS – 1960’s, but plagued by manufacturing
 PMOS in 1960’s (calculators)
 NMOS in 1970’s (4004, 8080) – for speed
 CMOS in 1980’s – preferred MOSFET technology
because of power benefits
 BiCMOS, Gallium-Arsenide, SiGe
 SOI, FinFET, Copper-Low K, …
7
 Giga-scale Integration
 1971: Intel 4004 (10µm, KHz, 2300 transistors
 2000: Intel Pentium-4 (~250nm/42M trans)
 2002: Intel Itanium (180nm/1-2+GHz)
 2015 - 2017: Intel Xeon (14-22nm/22-cores)
 2020/21: Intel Core-X (14nm/18-cores)
 53% compound annual growth for >50-yrs
 No other technology has grown so fast so long!!!
 Driven by transistor miniaturization/scaling
 Smaller is cheaper, faster, lower in power! 8
 Major Design Challenges
 Microscopic Issues  Macroscopic Issues
 ultra-high speeds  time-to-market
 power dissipation, supply rail  design complexity
drop (millions of gates)
 growing importance of  high levels of
interconnect abstractions
 noise, crosstalk  reuse and IP, portability
 reliability, manufacturability  systems on a chip (SoC)
 clock distribution  tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs

Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M 9
 Coping with Complexity
 How to design System-on-Chip?
 Billions of transistors
 Tens to hundreds of engineers
1. Structured Design
2. Design Partitioning

10
 Structured Design
 Hierarchy: Divide and Conquer
 Recursively decompose system into modules
 Regularity
 Reuse modules wherever possible
 Ex: Standard cell library
 Modularity: well-formed interfaces
 Allows modules to be treated as black boxes
 Locality
 Physical and Temporal 11
 Design Partitioning
 Architecture: User’s perspective, what does it do?
 Instruction set, registers
 MIPS, x86, Alpha, PIC, ARM, …
 Microarchitecture
 Single-cycle, multicycle, pipelined, superscalar?
 Logic: how are functional blocks constructed
 Ripple carry, carry lookahead, carry select adders
 Circuit: how are transistors used
 Fully complementary CMOS, pass transistors, domino
 Physical: chip layout of Datapath, memories, logic
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Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

Vin Vout

DEVICE
G

S D
n+ n+
13
 Why Silicon CMOS?
 Low power dissipation
 Significant mostly during switching (T or F?)
 High logic integration density
 Allows rail-to-rail output logic swings
 Provides symmetric transient response
 Capacitive nodes for dynamic storage
 Silicon is sand — plenty, cheap
 Si technology (infrastructure) & know-how (expertise)
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15
 Silicon (Si) Lattice
 Transistors built on silicon substrate
 Silicon is Group-IV material
 Forms crystal lattice with covalent bonds to four
neighbors
Si Si Si

Si Si Si

Si Si Si
 Dopants
 Pure Si is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants (impurities) increases conductivity
 Group V (e.g. As): donates extra electron to Si (n-type)
 Group III (e.g. B): accepts extra electron from Si (p-type)
 missing electron, termed hole (imagine “absence” of electron)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si p-type
n-type
 p-n Junctions
 Junction between p-type & n-type forms diode
 Current flows only in one direction
 Current flows from p- to n- type, as electrons from n to p
type (by convention)

p-type n-type

anode cathode
 Power Supply Voltage Rails
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power; but does it help or hurt reliability?
 (PS: Next Quiz – Discuss how low-VDD helps and hurts reliability)

 VDD = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.0V, …

 Transistors as Switches
 Can view MOSFET as voltage-controlled switch
 Voltage at gate controls current from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
 Inverter Layout

VDD

A Y

GND

A Y
 CMOS Inverter Layout
Out
In
metal1-poly via
metal1
polysilicon

metal2
VDD

pdiff
PMOS (4/.24 = 16/1)

NMOS (2/.24 = 8/1)

metal1-diff via

ndiff
GND
metal2-metal1 via
CMOS NAND Gate

ON
OFF
OFF
ON OFF
ON

1
Y
0
A ON
OFF

0
1
1
0
B OFF
ON
ON
OFF
CMOS NOR Gate

A
B
Y
 Technology Scaling
 Technology shrinks by ~0.7/generation
 Each generation can integrate 2x more
functionality; chip cost not increase
 Cost of a function decreases by 2x
 But …
 How to design chips with more functionality?
 Design engineering population does not double every
two years…
 Hence, need efficient design methods
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 Feature Size
nm
140 130
120
100 90
80 65
60 45
40 32
22
20
0
2001 2004 2007 2010 2013 2016
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Source: Intl. Technology Roadmap for Semiconductor (ITRS)
 Moore’s Law
 1965: Gordon Moore (Intel) plotted µP chip
transistor count over time
 Predicted number of transistors integrated on
die doubles every 18 months (exponential)
 Amazingly visionary – million transistor/chip
barrier crossed in the 1980’s
 2300 transistors, <1 MHz clock (Intel 4004) – 1971 MSI -LSI
 42 Million, 2 GHz clock (Intel P4) – 2001 VLSI
 140 Million transistor (HP PA-8500) ULSI
 Billion transistor – True systems-on-chip (SoC) era
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 Moore’s Law in Microprocessors
Transistors on leading microprocessors double every 1.5 - 2 years
1000

100
2X growth in 1.96 years!

10
P6
Transistors (MT)

Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year Courtesy, Intel
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Corollaries – Clock Frequency
 Many other factors grow exponentially
 E.g. clock frequency, processor performance
10000

1000 2X every 2 years

Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
29
Leading microprocessors frequency doubles every 2 years
Corollaries - DRAM Capacity
human memory
human DNA
100000000
64,000,000

10000000
4X growth every 3 years! 16,000,000 0.07 µm
4,000,000
0.1 µm
Kbit capacity/chip

1000000 1,000,000
0.13 µm
book 256,000 0.18-0.25 µm
100000
64,000
0.35-0.4 µm
16,000
10000 0.5-0.6 µm
4,000 encyclopedia
0.7-0.8 µm
1000 1,000 2 hrs CD audio
1.0-1.2 µm 30 sec HDTV
256
100 1.6-2.4 µm
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year
Corollaries - Die Size Growth
100

P6
Die size (mm)

486 Pentium ® proc

10
386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1970 1980 1990 2000 2010

Year
Courtesy, Intel 31
Side Effect - Power Dissipation*
Leading Microprocessors power continues to increase
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Power delivery and dissipation has become prohibitive

Courtesy, Intel 32
 Side Effect - Power Density*
10000
Rocket
Nozzle
1000
Nuclear
Reactor
Power Density (W/cm2)

100
Hot Plate
8086
10 4004 P6
8008 8085 386 Pentium® proc
286 486
8080
1

1970 1980 1990 2000 2010

Year Courtesy, Intel 33
 Design Productivity Trends
10,000 100,000

Logic Tr./Chip
(M)

1,000 10,000
Tr./Staff Month.
100 1,000
Logic Transistor per Chip
Complexity

(K) Trans./Staff - Mo.

10 58%/Yr. compounded 100
Complexity growth rate

1 10

Productivity
x x
0.1 1
x x 21%/Yr. compound
x x x
x Productivity growth rate
0.01 0.1

0.001 0.01
1989

2003

2005
1991

1993

1995

1997

1999

2001
1985

1987

2007
1981

1983

2009
Growing gap between design complexity & design productivity
Courtesy, ITRS Roadmap 34
 Summary/Recap
1. Brief Silicon Semiconductor Intro
 Lattice, doping, p-n junction …
2. Intro to CMOS Gates
 MOSFET as switch, layout …
3. Technology Scaling & Moore’s Law
 Corollaries – clock frequency, die size, DRAM capacity …
 Side effects – power consumption, power density …
4. Design Productivity & Abstraction …
 CAD tools, divide & conquer, abstraction through HDL …

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Questions?

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