Semiconductor

Chip design
CAD/EDA
Fab/Foundry

Digital enables abstraction

separation and noise suppression
.Device Level Abstraction
Process Design Kit (PDK) - Devices, Layers, Rules
Flavours - General purpose/ High speed/ Low power
RF/ Image sensor
Flash/ DRAM
Metal interconnect layers
.Circuit Level Abstraction
Schematics
SPICE
modify CDF parameters to optimize schematic
Length and Width of transistors
Number of Fingers
Capacitances and Resistances
Layout Editor, parasitic extraction, simulation
.Gate Level Abstraction
black-box gates
Boolean Functionality
Interface (i.e. pins or ports)
Delay and power consumption
Input and output capacitance
Size and geometry
.Module Level Abstraction
interconnected gates and circuits
tested for functionality
.Systems Level Abstraction
This abstraction level defines:
Registers
Instruction Sets
Control Blocks
Buses etc.
comply with standards and implement protocols
.Higher Level Abstraction
high level programming language

VLSI Design Styles

Full Custom design
everything at transistor level
Customization for optimized power, performance, area
High complexity = cost, time-to-market, high risk
Standard-cells based design
ASIC
HDL mapped to libraries
Simple, fast, reliable
Only Digital designs. Excess power, wirelength, etc.
Gate Array Design or Structured ASIC
implementation done with metal mask design and processing
Reduced number of masks àInexpensive
High percentage of overhead, limited speed
FPGA – Field Programmable Gate Array
Post silicon configurability, very inexpensive
High percentage of overhead. High cost per chip
Physical Design Flow

Standard-cells + Hard-IPs ---> Synthesizer <--- HDL code

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Place & Route <--- Floorplan
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Static Timing Analysis ---> DRC,
LVS, LEC, Gate-level sim

Tapeout

Trade-offs:
Speed
Power
Reliability
Cost

CMOS Process Flow

Lightly Doped Wafer
Grow Field Oxide
Define Wells
Grow Gate Oxide
Deposit Poly Gate
Etch Gates
Implant Source/Drain
Deposit Isolation
Oxide and Contacts
Deposit Metal 1
Deposit Isolation
Oxide and Via 1
Deposit Metal 2

Design Rules (DRC)

interface between designer and process engineer
.Intra layer rules :
only relating to a single layer
minimum widths, spacing, area, etc.
.Inter layer rules :
between two layers
minimum enclosures, extensions, overlaps, etc.
.Special rules :
non geometric rules
antenna rules, density, distance to welltap etc.

Well (p,n)
Active Area (n+,p+)
Select (p+,n+)
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via

Multi-finger devices
Latch-Up
The multiple n type and p type regions in the CMOS process create parasitic
BJT transistors
Unintentional "Thyristors"
short VDD and GND
To eliminate some latchup , distribute well/substrate contacts across the
chip

Bulk Contacts (Taps)

To ensure a constant body voltage across large areas
Taps make sure n-well is connected to VDD and p-substrate is connected to GND
Taps increase area, but essential to combat latch-up

Standard-cells:
Size
same specified height (multiple of track size)
VDD and GND rails with specified width
N well, p active, n active with specified width
Width is a multiple of the cell SITE minimum unit
Use fingers to implement wide transistors
Cell origin is set at (0,0)
Routing
Only Metal 1 and Poly are used for routing
Pins are defined in Metal 1 on cross point of Metal 2 tracks for easy
access
Half DRC pitch on sides to eliminate spacing violation

Good layout:
Good layout: dense and reliable
Meets the manufacturing DRC
Matches the circuit being built (LVS)

Inverter Fabrication Steps: (bottom up)

blank wafer (p-substrate)
form n-well
protective layer of SiO2
Spin on photoresist
Expose photoresist through n-well mask
Strip off exposed photoresist
Etch oxide with HF
Strip off remaining photoresist
n-Well formed with diffusion or ion implant
Strip off the remaining oxide using HF
Grow/deposit very thin layer of gate oxide
CVD of Si layer (poly)
Poly patterning
Self-aligned process
N-diffusion (use oxide layers)
P-diffusion (use oxide layers)
Contacts (use thick field oxide)
Metallization

Routing Grids:
Pins must be placed on the intersections of vertical & horizontal routing
grids
(except VDD/GND abutment pins)
ensure via-on-via Min. spacing