Layout Design Rules

MOS transistor

Design Rules: Bridges between

technology capability and
design considerations

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

Design Rules

Dual-Well Trench-Isolated CMOS

gate oxide

field oxide

Interface between the circuit designer and process engineer

Guidelines for constructing process masks

Unit dimension: minimum line width

Al (Cu)
TiSi2

p well

p+

scalable design rules: lambda parameter

absolute dimensions: micron rules

Rules constructed to ensure that design works even when small fab
errors (within some tolerance) occur

A complete set includes

SiO2

n well

p-

tungsten

p-epi
n+

SiO2

z
z
z

set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
is half of the minimum feature size in a given process (e.g.,
min. gate length).

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

Descriptions of a digital IC

CMOS Process Layers

entity inverter is
port (I1 :in Bit; O1 out Bit);
end inverter
HDL
Physical Layout
Circuit Schematic

Logic Gate
Wafer/die
EE 534 fall 2003 University of South Alabama

Design rules

EE 534 fall 2003 University of South Alabama

Physical
cross section

Layer

Color

Well (p,n)

Yellow

Active(p+,n+)

Green

Select(n+,p+)

Green

Poly

Red

Metal1

Blue

Metal2

Magenta

Contact to active

Black

Contact to poly

black

via

black

EE 534 fall 2003 University of South Alabama

Design rules

EE 534 fall 2003 University of South Alabama

Color

BW

Stick

Intra-Layer Design Rules

Contacts and Vias

Contacts:
Metal 1 to active
Metal 1 to poly 1
Metal 1 to poly 2

Vias:
Metal 2 to metal 1
Metal ? to metal ?
Stack Vias (not
always allowed):
Via directly on
top of contacts

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

Well and Select

Select

EE 534 fall 2003 University of South Alabama

Active with
select around it is
doped the same
type as the well

Active without
select is doped
the same type as
the substrate
EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

CMOS Inverter Layout

CMOS Inverter Layout

In

GND

GND

VDD

VDD

Out
p-substrate
n-select convention

n-well

Out

(a) Layout

Options
merged contacts
stack vias

Circuit Schematic
A

A
n

p-substrate
p+(substrate plug)

n+

p+ n+(well plug)

(b) Cross-Section along A-A

EE 534 fall 2003 University of South Alabama

In

EE 534 fall 2003 University of South Alabama

Field
Oxide

CMOS Transistor : Stacked Wide Transistors

Stacked Wide Transistors (W >> L)

CMOS Transistor : Ring Transistors (Wide)

Ring Transistors (W > L)

W >> L
Strong current drive
No bends
Source/drain share regions:
reduced capacitance

EE 534 fall 2003 University of South Alabama

Maximum W/L for a given CD (drain

inside).

No channel edge no edge effects.

Circular shape best (uniform channel

length, no corners), but not always
allowed.

EE 534 fall 2003 University of South Alabama

CMOS Transistor : Very Wide Waffle Transistors

Waffle Transistors (W >> L)

EE 534 fall 2003 University of South Alabama

CMOS Transistor : Long Serpentine Transistors

Long Transistors (W << L)

Large W/L for a given area.

Low parasitic source/drain

capaictances.

W << L (very weak current drive;

very large ON resistance)

Diagonal wires are useful, but not

always allowed.

One large gate covers the entire

serpentine channel

Low source, drain, and gate series

resistances.

Useful for load pull-up

transistors

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama

EE 534 fall 2003 University of South Alabama