CHAPTER 1: Introduction

1.1 Nanometer Designs

1.2 What is Static Timing Analysis?
1.3 Why Static Timing Analysis?
Crosstalk and Noise, 4
1.4 Design Flow
1.4.1 CMOS Digital Designs
1.4.2 FPGA Designs
1.4.3 Asynchronous Designs
1.5 STA at Different Design Phases
1.6 Limitations of Static Timing Analysis
1.7 Power Considerations
1.8 Reliability Considerations
1.9 Outline of the Book
CHAPTER 2: STA Concepts
2.1 CMOS Logic Design
2.1.1 Basic MOS Structure
2.1.2 CMOS Logic Gate
2.1.3 Standard Cells
2.2 Modeling of CMOS Cells
2.3 Switching Waveform
2.4 Propagation Delay
2.5 Slew of a Waveform
2.6 Skew between Signals
2.7 Timing Arcs and Unateness
2.8 Min and Max Timing Paths
2.9 Clock Domains
2.10 Operating Conditions
CHAPTER 3: Standard Cell Library
3.1 Pin Capacitance
3.2 Timing Modeling
3.2.1 Linear Timing Model
3.2.2 Non-Linear Delay Model
Example of Non-Linear Delay Model Lookup, 52
3.2.3 Threshold Specifications and Slew Derating 53
3.3 Timing Models - Combinational Cells
3.3.1 Delay and Slew Models
Positive or Negative Unate, 58
3.3.2 General Combinational Block
3.4 Timing Models - Sequential Cells
3.4.1 Synchronous Checks: Setup and Hold 6
Example of Setup and Hold Checks, 62
Negative Values in Setup and Hold Checks, 64
3.4.2 Asynchronous Checks
Recovery and Removal Checks, 66
Pulse Width Checks, 66
Example of Recovery, Removal and Pulse Width Checks, 67
3.4.3 Propagation Delay
3.5 State-Dependent Models
XOR, XNOR and Sequential Cells, 70
3.6 Interface Timing Model for a Black Box
3.7 Advanced Timing Modeling
3.7.1 Receiver Pin Capacitance
Specifying Capacitance at the Pin Level, 77
Specifying Capacitance at the Timing Arc Level, 77
3.7.2 Output Current
3.7.3 Models for Crosstalk Noise Analysis
DC Current, 82
Output Voltage, 83
Propagated Noise, 83
Noise Models for Two-Stage Cells, 84
Noise Models for Multi-stage and Sequential Cells, 85
3.7.4 Other Noise Models
3.8 Power Dissipation Modeling
3.8.1 Active Power
Double Counting Clock Pin Power?, 92
3.8.2 Leakage Power
3.9 Other Attributes in Cell Library
Area Specification, 94
Function Specification, 95
SDF Condition, 95
3.10 Characterization and Operating Conditions
What is the Process Variable?, 96
3.10.1 Derating using K-factors
3.10.2 Library Units
CHAPTER 4: Interconnect Parasitics
4.1 RLC for Interconnect
T-model, 103
Pi-model, 104
4.2 Wireload Models
4.2.1 Interconnect Trees
4.2.2 Specifying Wireload Models
4.3 Representation of Extracted Parasitics
4.3.1 Detailed Standard Parasitic Format
4.3.2 Reduced Standard Parasitic Format
4.3.3 Standard Parasitic Exchange Format
4.4 Representing Coupling Capacitances
4.5 Hierarchical Methodology
Block Replicated in Layout, 120
4.6 Reducing Parasitics for Critical Nets
Reducing Interconnect Resistance, 120
Increasing Wire Spacing, 121
Parasitics for Correlated Nets, 121
CHAPTER 5: Delay Calculation
5.1 Overview
5.1.1 Delay Calculation Basics
5.1.2 Delay Calculation with Interconnect
Pre-layout Timing, 125
Post-layout Timing, 126
5.2 Cell Delay using Effective Capacitance
5.3 Interconnect Delay
Elmore Delay, 132
Higher Order Interconnect Delay Estimation, 134
Full Chip Delay Calculation, 135
5.4 Slew Merging
5.5 Different Slew Thresholds
5.6 Different Voltage Domains
5.7 Path Delay Calculation
5.7.1 Combinational Path Delay
5.7.2 Path to a Flip-flop
Input to Flip-flop Path, 143
Flip-flop to Flip-flop Path, 144
5.7.3 Multiple Paths
5.8 Slack Calculation
CHAPTER 6: Crosstalk and Noise
6.1 Overview
6.2 Crosstalk Glitch Analysis
6.2.1 Basics
6.2.2 Types of Glitches
Rise and Fall Glitches, 152
Overshoot and Undershoot Glitches, 152
6.2.3 Glitch Thresholds and Propagation
DC Thresholds, 153
AC Thresholds, 156
6.2.4 Noise Accumulation with Multiple Aggressors 160
6.2.5 Aggressor Timing Correlation
6.2.6 Aggressor Functional Correlation
6.3 Crosstalk Delay Analysis
6.3.1 Basics
6.3.2 Positive and Negative Crosstalk
6.3.3 Accumulation with Multiple Aggressors 169
6.3.4 Aggressor Victim Timing Correlation 1
6.3.5 Aggressor Victim Functional Correlation 171
6.4 Timing Verification Using Crosstalk Delay
6.4.1 Setup Analysis
6.4.2 Hold Analysis
6.5 Computational Complexity
Hierarchical Design and Analysis, 175
Filtering of Coupling Capacitances, 175
6.6 Noise Avoidance Techniques
CHAPTER 7: Configuring the STA Environment 179
7.1 What is the STA Environment?
7.2 Specifying Clocks
7.2.1 Clock Uncertainty
7.2.2 Clock Latency
7.3 Generated Clocks
Example of Master Clock at Clock Gating Cell Output, 194
Generated Clock using Edge and Edge_shift Options, 195
Generated Clock using Invert Option, 198
Clock Latency for Generated Clocks, 200
Typical Clock Generation Scenario, 200
7.4 Constraining Input Paths
7.5 Constraining Output Paths
Example A, 205
Example B, 206
Example C, 206
7.6 Timing Path Groups
7.7 Modeling of External Attributes
7.7.1 Modeling Drive Strengths
7.7.2 Modeling Capacitive Load
7.8 Design Rule Checks
7.9 Virtual Clocks
7.10 Refining the Timing Analysis
7.10.1 Specifying Inactive Signals
7.10.2 Breaking Timing Arcs in Cells
7.11 Point-to-Point Specification
7.12 Path Segmentation
CHAPTER 8: Timing Verification
8.1 Setup Timing Check
8.1.1 Flip-flop to Flip-flop Path
8.1.2 Input to Flip-flop Path
Input Path with Actual Clock, 240
8.1.3 Flip-flop to Output Path
8.1.4 Input to Output Path
8.1.5 Frequency Histogram
8.2 Hold Timing Check
8.2.1 Flip-flop to Flip-flop Path
Hold Slack Calculation, 253
8.2.2 Input to Flip-flop Path
8.2.3 Flip-flop to Output Path
Flip-flop to Output Path with Actual Clock, 257
8.2.4 Input to Output Path
8.3 Multicycle Paths
Crossing Clock Domains, 266
8.4 False Paths
8.5 Half-Cycle Paths
8.6 Removal Timing Check
8.7 Recovery Timing Check
8.8 Timing across Clock Domains
8.8.1 Slow to Fast Clock Domains
8.8.2 Fast to Slow Clock Domains
8.9 Examples
Half-cycle Path - Case 1, 296
Half-cycle Path - Case 2, 298
Fast to Slow Clock Domain, 301
Slow to Fast Clock Domain, 303
8.10 Multiple Clocks
8.10.1 Integer Multiples
8.10.2 Non-Integer Multiples
8.10.3 Phase Shifted
CHAPTER 9: Interface Analysis
9.1 IO Interfaces
9.1.1 Input Interface
Waveform Specification at Inputs, 318
Path Delay Specification to Inputs, 321
9.1.2 Output Interface
Output Waveform Specification, 323
External Path Delays for Output, 327
9.1.3 Output Change within Window
9.2 SRAM Interface
9.3 DDR SDRAM Interface
9.3.1 Read Cycle
9.3.2 Write Cycle
Case 1: Internal 2x Clock, 349
Case 2: Internal 1x Clock, 354
9.4 Interface to a Video DAC
CHAPTER 10: Robust Verification
10.1 On-Chip Variations
Analysis with OCV at Worst PVT Condition, 371
OCV for Hold Checks, 373
10.2 Time Borrowing
Example with No Time Borrowed, 379
Example with Time Borrowed, 382
Example with Timing Violation, 384
10.3 Data to Data Checks
10.4 Non-Sequential Checks
10.5 Clock Gating Checks
Active-High Clock Gating, 396
Active-Low Clock Gating, 403
Clock Gating with a Multiplexer, 406
Clock Gating with Clock Inversion, 409
10.6 Power Management
10.6.1 Clock Gating
10.6.2 Power Gating
10.6.3 Multi Vt Cells
High Performance Block with High Activity, 416
High Performance Block with Low Activity, 417
10.6.4 Well Bias
10.7 Backannotation
10.7.1 SPEF
10.7.2 SDF
10.8 Sign-off Methodology
Parasitic Interconnect Corners, 419
Operating Modes, 420
PVT Corners, 420
Multi-Mode Multi-Corner Analysis, 421
10.9 Statistical Static Timing Analysis
10.9.1 Process and Interconnect Variations
Global Process Variations, 423
Local Process Variations, 424
Interconnect Variations, 426
10.9.2 Statistical Analysis
What is SSTA?, 427
Statistical Timing Libraries, 429
Statistical Interconnect Variations, 430
SSTA Results, 431
10.10 Paths Failing Timing?
No Path Found, 434
Clock Crossing Domain, 434
Inverted Generated Clocks, 435
Missing Virtual Clock Latency, 439
Large I/O Delays, 440
Incorrect I/O Buffer Delay, 441
Incorrect Latency Numbers, 442
Half-cycle Path, 442
Large Delays and Transition Times, 443
Missing Multicycle Hold, 443
Path Not Optimized, 443
Path Still Not Meeting Timing, 443
What if Timing Still Cannot be Met, 444
10.11 Validating Timing Constraints
Checking Path Exceptions, 444
Checking Clock Domain Crossing, 445
Validating IO and Clock Constraints, 446
APPENDIX A: SDC
A.1 Basic Commands
A.2 Object Access Commands
A.3 Timing Constraints
A.4 Environment Commands
A.5 Multi-Voltage Commands
APPENDIX B: Standard Delay Format (SDF) 467
B.1 What is it?
B.2 The Format
Delays, 480
Timing Checks, 482
Labels, 485
Timing Environment, 485
B.2.1 Examples
Full-adder, 485
Decade Counter, 490
B.3 The Annotation Process
B.3.1 Verilog HDL
B.3.2 VHDL
B.4 Mapping Examples
Propagation Delay, 502
Input Setup Time, 507
Input Hold Time, 509
Input Setup and Hold Time, 510
Input Recovery Time, 511
Input Removal Time, 512
Period, 513
Pulse Width, 514
Input Skew Time, 515
No-change Setup Time, 516
No-change Hold Time, 516
Port Delay, 517
Net Delay, 518
Interconnect Path Delay, 518
Device Delay, 519
B.5 Complete Syntax
APPENDIX C: Standard Parasitic Extraction Format (SPEF) 531
C.1 Basics
C.2 Format
C.3 Complete Syntax