https://www.embedded.

com/asynchronous-reset-synchronization-and-distribution-
challenges-and-solutions/

Lack of coordination between asynchronous resets and synchronous logic clocks

=> intermittent failures on power up

Reset brings synchronous circuitry to known state after power up

Reset is mostly required for the control logic and may be eliminated from the
data path logic
reset can be asynchronous or synchronous

Coordinate async reset release with sync clock signal to eliminate synchronization
failures

Handle reset distribution like CTS

=> reset require similar area and routing resources

Synchronous reset
requires an active clock,
incurs certain clock-cycle related latency and
may impact the timing of the data paths

but, is deterministic and do not incur metastability

Asynchronous reset
does not require an active clock,
has a lower latency than a synchronous reset and
can exploit special flip-flop input pins that do not affect data path timing

may cause metastability in flip-flops

must be made directly accessible to enable DFT
may incur reliability problems in rad-hard applications (susceptible to
Single Event Transient phenomena)

Asynchronous reset drivers

external ports,
depending on power supply status (RC circuits, watchdog devices),
manual reset buttons and
external masters, such as microprocessors

Asynchronous reset is compulsory in cases like clock-gated/power-gated logics

For Asynchronous reset,

relative timing between clock and reset can be ignored during reset assertion
reset assertion affects flip-flop output Q within a deterministically
bounded time
ie., only propagation delay (TR-pd ) and regardless of clock signal CLK
but, reset release must be synchronized to the clock
setup and hold timing conditions must be satisfied for the RST port
relative to the clock port CLK
violation of the setup and hold conditions for the RST port (aka reset
recovery and removal timing) cause metastability

Clock and reset skew can arise due to

design variations - unequal wire length, unequal load, IR drop
process variations - buffer and wire

skew can result in reset triggering at different times - breaking

functionality

Reset synchronizers