Name : SHAIK SUHIL IRSHAD

REG.NO: 18BEC2007
DIGITAL ASSIGNMENT

Problem 1.
Discuss about the Pulsed Latches with its schematic and output
waveform. Highlight the advantages over the conventional Laches
Ans :
Pulsed latches (Spinner cells) are an alternative to flip-flops for
synchronous memorization, which had seen a number of failed attempts
over the years. Their industrialization until now was lacking. On the one
hand, a flip-flop allows capturing data on an active edge (high or low) of
a clock signal.
A latch can capture data during the sensitive time determined by the
width of clock waveform. If the pulse clock waveform triggers a latch, the
latch is synchronized with the clock similarly to edge-triggered flip-flop
because the rising and falling edges of the pulse clock are almost
identical in terms of timing. With this approach, the characterization of
the setup times of pulsed latch are expressed with respect to the rising
edge of the pulse clock, and hold times are expressed with respect to the
falling edge of the pulse clock. This means that the representation of
timing models of pulsed latches is similar to that of the edge-triggered
flip-flop. The pulsed latch requires pulse generators that generate pulse
clock waveforms with a source clock. The pulse width is chosen such that
it facilitates the transition. The following diagram represents a simple
pulse generator and the associated pulse waveform.
Explain the operation of Synchronous andAsynchronous Resettable
latches with its schematic.

Ans:

A Reset is required to initialize a hardware design forsystem operation and to

force an ASIC into a known state for simulation. A reset simply changes the
state of the device/design/ASICto a user/ designer defined state. There are
two types of reset, they areSynchronous reset and Asynchronous reset. Reset
is usually applied atthe beginning of time for simulation and is usually applied
at power-up for real hardware and Reset may be applied during operation by
watchdog circuits .
There are two types of reset: synchronous and asynchronous.
Synchronous reset signals must be stable for a setup and hold time around
the clock edge while asynchronous reset is characterized by apropagation
delay from reset to output.
Asynchronous reset requires gating both the data and the feedback to force
the reset independent of the clock. Asynchronous reset forces Q low
immediately, while synchronous reset waits for the clock.
Synchronous reset simply requires ANDing the input D with reset. The tristate
NAND gate can be constructed from a NAND gate in series witha clocked
transmission gate.

Problem 3.
Explain the operation of Enabled latches with itsschematic.
Solution 3 –
Latch is an electronic logic circuit with two stable states. Latch has a
feedback path to retain the information. Hence a latch canbe a memory
device. Latch can store one bit of information as long asthe device is
powered on. When enable is asserted, latch immediately changes the stored
information when the input is changed i.e. they arelevel triggered devices. It
continuously samples the inputs when the enable signal is on.
Generally, latches are transparent i.e. the output changes immediately when
there is a change in the input. But for many applications, it is desirable to
have an isolated period where the output doesn’t change even when there is
a change in the input. During this period, the outputs are said to be truly
‘latched’. This can be achieved with the use
of an extra input (enable or clock or gate).

Sequencing elements often accept an enable input. When enable en is low, the
element retains its state independently of the clock. The enablecan be
performed with an input multiplexer or clock gating. The input multiplexer
feeds back the old state when the element is disabled. The multiplexer adds
area and delay.
Clock gating does not affect delay from the data input and the AND gate can
be shared among multiple clocked elements. Moreover, it significantly
reduces power consumption because the clock on the disabled element does
not toggle. However, the AND gate delays the clock, potentially introducing
clock skew. There are several techniques to minimize the skew by building
the AND gate into the final buffer of the clock distribution network. en must
be stable while the clock is highto prevent glitches on the clock.