SCAN INSERTION PART 2

1. How you take care of design while inserting scan chain?

The following list includes the successful adoption of scan techniques:

 Handle internal tristate buses with care and avoid bus contention by design.
 Make all clocks and asynchronous resets come from chip pins during scan mode.
 Ensure that all scan elements on a scan chain are in the same clock domain.
 Know the requirements and limitations of your chip testers.
 Handle mixing flip-flops triggered off different edges of the clock with care.
 Break all combinational-logic feedback loops.
 Handle all no scan elements with care.
 Avoid design practices that lead to non scannable elements.
 Handle multiple clock domains with care to avoid potential timing problems.
 Plan chip-level scan issues before you start block-level design.
2. How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?
Negative edge flops are placed in the first position in scan chains .If negative edge flops are in
between the scan chains, it leads to setup and hold violations. Since at the intersection of positive and
negative flop the data will not be captured. Since at single pulse data launch and capture is not
possible. We add lockup latches when scan chains are stitched from positive edge to negative edge to
avoid hold issues.

3. How asynchronous and synchronous resets are handled for scan?

Design with async reset. This is async in assertion and sync in de-assertion. Also, the output
of the synchronizers is ORed with a top level dft resest disable port which behaves the same way
as scan enable. This is done to avoid any reset issues during shift. In capture, the reset can toggle
to achieve coverage on the synch paths.
4. How tri-states are handled during scan?
Tristates mainly causes Bus Contention and to avoid bus contention we add bus keeper circuit
to the design.
5. How does scan chain works? Explain with an example?
In general, a scan chain is formed out of scan cells belonging to a single clock domain. For
clock domains that contain a large number of scan cells, several scan chains are constructed, and a
scan-chain balancing operation is performed on the clock domain to reduce the maximum scan-chain
length. Scan chains are balanced for avoiding extra post shift bits

 Scan chain is a technique used in design for testing. The objective is to make testing
easier by providing a simple way to set and observe every flip-flop in an IC. The basic
structure of scan include the following set of signals in order to control and observe
the scan mechanism.
 Figure. Scan chain in state flip-flop block

Figure shows the state flip-flops with scan chain in a sequential circuit; other blocks are not
shown for clarity. As discussed, flip-flops with scan-chain take inputs from two parts of the
circuit (i) next state function block (when operating normally) and (ii) from the previous flip-
flop in the chain (when in test mode); the first flip-flop in the scan chain takes input from a
primary input “Scan in”. So in state flip-flop block with scan chain, all the flip-flops must have
a 2X1 multiplexer. One input is from the next state function block and the other is from the
previous flip-flop in the chain. The control input called mode basically decides the mode of
operation; 1 for scan-chain and 0 for normal operation. Figure shows this concept for a circuit
with three flip-flops.

6. Can we have the shift frequency same as functional frequency?

The maximum shift frequency will depend on what is the maximum peak power, the
chip can support.  When you are shifting the data on the scan chain, all the flops in the chains
are operational the same time. The peak power requirement goes high, also too much of heat
is generated, if you don’t account for it the chip will burn up. In the functional mode, you will
never get a chance where all the flops will be operational at the same time.
7. How to solve setup and Hold violations in the design?
For hold one way is to insert buffers. For setup only way to upsize the cell and tweak
the skew. Or reduce the levels of logic from reg2reg, use fasted cells, swap pins, slow down
the clock, or etc. and we also insert lockup latches to solve setup and hold violations.
8. Give three Clock drc rules and how to fix them?
1. Clock not controllable from the top. (Use mux to control the same) 
2. When all the clocks are in off state, the latches should be transparent (add logic to make
them transparent) 
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data
may be affected by new captured data. (for FASTSCAN : clock off simulation on and for
TetraMAX : set atpg -resim_basic_scan_pattern) 
9. How to fix the hold/setup violation in scan path (Q to SI path)?
 always some left, so your process has to include a step where the post-route netlist is
re-analyzed for timing (both mission and scan mode), and any hold violations left in the scan
path are manually fixed If the violations are small, as in most designs with well balanced
clock trees, the place and route tools can generally fix these by adding small buffers/inverters.
Some smart scan reordering tools will take a slightly farther scan flip-flop to avoid hold
problems. If the violations are big, due to large clock skews, the best way to solve this is to add
a data lockup latch. The tools look first to reduce congestion, by reducing the number of clock
buffers in the scan path, which will minimize hold time violations, but there are.
10. What the major problem faced in dft with tri-state buffers and how is it resolved?
 The major problem is from the tester end, not all testers are able to measure Z. 
 For the IDDQ vectors, there can be no Z in the design, there is quite a lot of current
when a pin is in Z state. A floating bus that is a bus with z on it will drain too much of
current and hence loosing the objective of the iddq vectors. 
 Next these tri-state buffers are generally used for sharing the bus, so there has to be a
dft logic so there is no contention on these bus during test.
11. What you mean by scan chain reordering?
During placement, the optimization may make the scan chain difficult to route due to
congestion. Hence the tool will re-order the chain to reduce congestion. This sometimes
increases hold time problems in the chain. To overcome these buffers may have to be inserted
into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap
cell from different clock domains. Because of scan chain reordering patterns generated earlier
is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.
12. By full scan methodology do we mean that every single flop in the design is a part of
the scan chain? And if we have multiple scan chains instead of one, as it is in present
designs, can it still be called full scan methodology?
Full scan means every flip-flop, but in the real scenario, many flops can be
unscanned, and the design is still considered full scan. In some cases, the ATPG tool can test
through unscanned flops without a major impact to fault coverage. Designs using one or many
scan chains are equally valid as full scan designs.
LSSD is really a sub-specialty in the industry as a whole only a few companies use it,
but it is effective. For scan purposes, it does not suffer from the hold time issues that mux-scan
normally does, but area-wise, it's not as good.
Clock-scan uses a separate scan-clock for each flop - I've never seen it used in
industry, but that's just me. The problem with it is that you must route two clock trees around
the chip instead of one - a virtual show-stopper in these days of congested routing.
13. Apart from the conventional mux FF scan architecture, there are many others like
the Level Sensitive scan and the clocked scan etc. How are these better or worse than
the muxed FF technique?

LSSD is really a sub-specialty in the industry as a whole only a few companies use it,
but it is effective. For scan purposes, it does not suffer from the hold time issues that mux-
scan normally does, but area-wise, it's not as good. 
Clock-scan uses a separate scan-clock for each flop. The problem with it is that you must
route two clock trees around the chip instead of one - a virtual show-stopper in these days of
congested routing.
14. I have 3 types of flops in my design. 1. CLK domain posedge 2. CLK domain negedge
3. RCO_CLK domain posedge only. Is it feasible/possible to put them in 1 scan-chain?
Yes, it is possible. 
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge
CLK domain flip-flops before posedge CLK domain flip-flops, i.e., negedge CLK FFs are
closer to scan input, and posedge CLK FFs are closer to scan output. 
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a
significantly larger clock tree than RCO_CLK clock tree, then it is better to put RCO_CLK
domain FFs at the end of the chain. Otherwise, you may need to skew your clock timing on
the ATE. 
This means your chain will look like this: 
Scan In -> negedge CLK -> posedge CLK -> RCO_CLK -> Scan Out
15. In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -
ve edge triggered how it behaves?
For designs with both positive and negative clocked flops, the scan insertion tool will
always route the scan chain so that the negative clocked flops come before the positive edge
flops in the chain. This avoids the need of lockup latch.

For the same clock domain the negedge flops will always capture the data just captured into
the posedge flops on the posedge of the clock.
For the multiple clock domains, it all depends upon how the clock trees are balanced. If the
clock domains are completely asynchronous, ATPG has to mask the receiving flops