1. How much real time experience do you have in DFT?

2. In project, what you did like ATPG or simulation?

3. In ATPG, what kind of fault did you get?
4. How did you improve the coverage in ATPG?
5. What is the actual flop count and scan chain length in your design?
6. After compression, how much is the chain lenght?
7. Have you ever worked on GLS and JTAG?
8. What is your scan clock frequency and at speed frequency?
9. How much coverage did you get in ATPG?
10. Have you transferred the generated pattern to others person/ team?
11. If a pin value ties to X, then during ATPG, How can it affect the coverage?
12. Due to the Clock domain crossing, In ATPG can we see any coverage loss and if yes then
how will handle it?
13. If a data pin and clk pin of a flop is driven by the same pin then what would it cause and how
to handle this problem?
14. If we have pre-scan inserted net list and later also we have to perform scan insertion for some
of its remaining part then how to take care of this and how can be stich pre-existing chains
with new scan chains ?
15. If parallel simulation is failing, then what can be the cause of it and how will it be resolved?
16. During scan compressed serial pattern simulation, if we find any mismatches then what is the
good approach to detect and clear it?
17. No. of patterns generated by the ATPG tool, depends upon which parameters?

Q1.What is compression ratio and how did you decide it?

Q2. How much was the chain length in your design?
Q3. Explain EDT and why we need the EDT?
Q4. What are the inputs and outputs of the EDT block?
Q5. What is the use of edt_update signal? And when it must be required in the testproc file?
Q6. Explain the testproc file? What are all the events it contains and explain them ?
Q7. Why do we need of edt_clock signal? Can edt_clock and the scan clock be the same
and if No the
Explain it?
Q8. Why we need OCC in our design?
Q9. How many OCC was present in your design and what are all inputs required for the
OCC?
Q10. Where we need to define the OCC, whether it can be define in testproc file or
elsewhere, explain?
Q11. How did you define the OCC and how can you make sure for getting the correct
capture pulse?
Q12. Why we need two capture pulses and in what case it can be more than two, explain?
Q13. What do mean by the sequential depth, elaborate this term?
Q14. What was the slow clk freq. and Fast clk freq. in your design?
Q15. Where you should define the clock to get it at the proper frequency suppose you need
200 MHz
clock?
Q16. How much coverage did you get in your design?
Q17. What did you do to get the maximum coverage in your design, explain your debugging
process?
Q18. What do you understand with Uncontrolled and unobserved fault, and why do they
appear in the
report?
Q19. How many types of DRC’s you have seen?
Q20. Explain T3 and T5 drc’s and how these can be resolved?
Q21. Did you face any D1 and D2 violation and what can be the cause of these and how to
remove?
Q22. What you did to resolve D1 violation?
Q23. Do we need to control the async_reset during scan insertion? Why? And how did you
do it?
Q24. What do know about a lockup latch, explain? And In what scenario we do need of it?
Q25. Do we need the lockup latch if the Trailing edge flop is followed by the leading edge
flop, explain
the scenario?
Q26. What do know about the Hold violation?
Q27. Explain the clock domain crossing?
Q28. What do know about the clock synchronizer and why we need of it?
Q29. What is NCP? And in what practical scenarios we should use NCP, explain?
Q30. Explain the combinational feedback loop and why do we need to control it?