Automatic Test Pattern

Generation
Srivatsa Mutukuri
Contents:
 Introduction to ATPG
 Fault Modeling
 Fault Classes
 Atspeed Testing
 Transition
 Path Delay
 Introduction to ATPG Tools
 Coverage Analysis
 ATPG Commands in Mentor Tools
 Patterns
Introduction to ATPG
 Automatic Test Pattern Generation is a process used in semiconductor electronics
device testing.
 The test patterns required to check a device for faults are automatically generated by
program
 Types of ATPG
 Combinational ATPG
 Sequential ATPG
 Multiload ATPG
Fault Modeling
 Necessity of Fault Modeling
 Fault Models
 Fault Detection
 Fault Collapsing
Why Fault Modeling?
 Identifies the targeted faults
 Model faults most likely to occur
 limits the scope of test generation
 Creates test patterns only for the modelled faults
 Makes effectiveness measurable
 Fault coverage can be computed for specific test patterns to reflect its
effectiveness
 Makes analysis easy
 Associates specific defects with specific test patterns
Fault Models
 Stuck At Faults
 Delay Faults
 Common Fault Models
 Bridging Faults
 Transistor short/open Faults
 Functional Faults
 Memory Faults
 PLA Faults
Stuck At Faults
 Single Stuck At faults

 Only one line is Faulty

 Fault line is permanently set to 0 or 1
 Fault can be at an input or output of a
gate

 Multiple Stuck At faults

 Several Stuck at faults occur at the

same time
 For a circuit with k lines
 2k single stuck at faults
 multiple stuck at faults
Delay Faults
 Transition Delay Faults :
 Assumes a large/gross delay is present at a circuit node
• Stuck-to-rise (0 - 1)
• Stuck-to-fall (1 - 0)
 Irrespective of which path the effect is propagated the gross delay defect
will be late arriving at an observable point.
 Needs to two test vectors
• Initialization vector to excite the circuit
• Test vector for launching the transition
 Path Delay Faults :
 Propagation Delay of the path exceeds the clock interval
 Number of paths grow exponentially with number of gates
Fault Detection
 Fault Excitation
 Fault Propagation
 Line Justification

Fault Excitation or Activation :

• Activating the fault site by forcing an

opposite value
Fault Propagation :

• Propagates the faulty value to the observable point / primary outputs

Line Justification :

 To create a test patterns or to justify the generated patterns

Fault Collapsing
 Fault Equivalence
 Fault Dominance
 Checkpoint

Fault Equivalence :

 If all the test vectors of one fault (F1) also detects the other fault (F2).
 If F1 & F2 are said to be equivalent then corresponding faulty functions are
identical.
Fault Equivalence Rules :
Fault Equivalence Example :

Equivalence Collapsing :

 Faults in the boldface are

removed
 If two faults are said to be
equivalent then we can
consider one fault among
them and generate the
patterns
Fault Dominance :
 If all the test vectors of F1 detects
the other fault F2 then F2 is
dominating the F1
Dominance Fault Collapsing :
 When F2 dominates F1, then F2 is
removed from the fault list.
 During Dominance collapsing it is
sufficient to consider only the input
faults of Boolean gates
 If two faults dominates each other
they are equivalent
Dominance Example :
Checkpoints :

 Primary inputs and fanout branches of a combinational circuit are called

checkpoints
 A test set that detects single (multiple) stuck at faults on all checkpoints of a
combinational circuit, also detects all single (multiple) stuck at faults in that
circuit
Fault Classes :

 Testable
 DT : Detected
 PD : Possibly Detected
 AU: ATPG Untestable
 UD: Undetected
 Untestable
 UU: Unused
 BL : Blocked
 TI : Tied
 RE : Redundant
 Testable Faults : Faults can be tested by some patterns
 Detected (DT) :
 The Faults which are detected during the ATPG process are categories under DT
 det_simulation(DS): The faults detected when the tools performs simulation
 det_implication(DI): The faults detected when the tool performs learning analysis
 Posdet (PD) :
 The Possible detected, faults includes all the faults that fault simulation identifies as possible detected
 posdet_testable(PT): Potentially detectable posdet faults. With higher abort limit we can reduce the number of these
faults
 posdet_untestable(PU): These are proven ATPG untestable and hard undetectable faults.
 ATPG Untestable (AU)
 This fault class includes all the faults for which test generator unable to find the pattern to create a test.
 Testable faults become ATPG untestable faults because of constraints or limitations, placed on the ATPG tool such as
pin constraint or an insufficient sequential depth.
 This faults may be detectable, if we remove some constraint, or change some limitations on the test generator
 UNDETECTED (UD): 
 This fault class includes the undetected faults that cannot be proven untestable or atpg_untestable
 uncontrolled(UC)
 unobserved(UO)
 All the testable faults prior to ATPG are put in the UC category. Faults that remain UC or UO after APTG aborted,
which means that with higher abort limit may reduce the UC and UO fault class
 Untestable :
 The faults for which no pattern exit to either detect or possible detect them.
 These faults cannot cause any functional failures.
 The tools excludes them while calculating the test coverage.
 Unused (UU) :
 Any floating pins not used in the design come under UU fault
 The unused faults class includes all the faults on circuit unconnected to any
observation point
 Tied (TI) :
 This faults includes faults on gates where the point of the faults is tied to a value identical to the fault stuck value

 Blocked (BL):
 Due to tied logic in the design few faults are blocked and these are categories into Blocked faults. By adding the
observable test point we can increase the coverage report.

 Redundant (RE):
 The faults which are undetectable by the tool by any pattern , are classified as redundant faults
Tester Clock Frequency Vs Fault Model
 Path Delay : 100 MHz – 1 GHz
 Transition Delay : 1-100 MHz
 Stuck – at : 1MHz
Atspeed Testing :
 The basic operation of at-speed scan testing involves loading the scan chains
at a slow clock rate and then applying two clock pulses at the functional
frequency.
 The first pulse causes a transition to start propagating from a scan-cell.
 The second pulse captures the scan cell value at the end of the path being
tested.
 Two types of testing
 Launch off Capture (LOC)
 Launch off Shift (LOS)
 Launch off Capture :
 The scan chain is loaded and then placed in
functional/capture mode by forcing
scan_enable (SE) to 0.
 An extra cycle is added to the test pattern
that has no activity to ensure that the
scan_enable completely settles.
 Next, two pulses are generated to launch
and capture the transition.
 Launches the transition pulse in the
functional mode of operation, so it is likely
to propagate transitions along paths that are
real functional paths.
 Often, the coverage report from broadside
pattern ATPG can be 10% lower than
standard static stuck-at patterns.
 Launch off Shift :

 Launch occurs during the last shift

while loading the scan chain
 To load the starting value for a
transition directly to the scan cell
one shift before the last and then
load the transition value in the last
shift.
 LOS recovers higher coverage ,
fewer patterns , faster ATPG
runtimes compared to LOC 
Why LOC?
 Difficulty to make the circuit change from shift mode to
functional/capture mode between the last shift and functional clock
pulse.
 Clock routing complexity issues
ATPG Tool Flow:
Inputs :
 Scan Inserted design netlist (with or
without compression)
 Test proc files
 Dofiles
 Lib Files

Outputs :
 Patterns in STIL or .V format
 Fault report files
Fast scan Modes :
 Setup Mode
 Analysis Mode
Unix > tessent –shell
Setup > set_context patterns –scan // Invokes the Fastscan tool
Setup > read_cell_library adk.tcelllib //read the lib file
Setup > read_verilog netlist.v // reads the scan inserted netlist
Setup > set_current_design // loads the top_module of the design
Setup >dofile scan_verify*.dofile //reads the dofile, dofile file contains clock, testproc file details
Setup > check_design_rules // checks for the DRC’s, if there are no DRC’S enters into the Analysis mode
Analysis > set_fault_type stuck // adding the stuck at fault type
Analysis > add_faults –all // adding all faults at all fault sites in the design
Analysis > create_patterns // generates the test patterns for specified fault type
Analysis > report_statistics –detail // generates the detailed fault classes report
Analysis >write_patterns netlist_stuck_chain.stil –stil –chain // generates the chain stil patterns
Analysis >write_patterns netlist_stuck_serial.stil –stil –serial // generates the serial stil patterns
Analysis >write_patterns netlist_stuck_parallel.stil –stil –parallel // generates the serial stil patterns
Analysis >write_patterns netlist_stuck_chain.v –verilog –chain // generates the chain stil patterns
Analysis >write_patterns netlist_stuck_serial.v –verilog –serial // generates the serial stil patterns
Analysis >write_patterns netlist_stuck_parallel.v –verilog –parallel // generates the serial stil patterns
ATPG Testproc :
Coverage Analysis :
Test Coverage =

Fault Coverage =

Steps to Debug Fault Coverage :

 Modify the Pin Constraints

 Target the AU Faults
 Change the Sequential Depth
 Increase the abort limit
ATPG DRC’s :

 K Rules : EDT Rules

 Applies to the design with EDT Logic
 P Rules : Procedure Rules
 Ensures Testproc file is syntactically and Functionally correct
 T Rules : Scan Chain Tracing Rules
 Traces the scan chains to identify scan cells and all memory elements associated with scan cells
 S Rules : Scannability Rules
 Checks to ensure that scan tool can safely convert a sequential element to a scan element
 W Rules : Timing Rules

• Please refer Tessent Shell Reference manual for

detailed information of DRC’S
 Tracing Violation : Tracing of a scan chains from
output pin to scan input pin, if the tool is unable to
trace back it will through a T Violation
 Case I :
 In this case as shown below after tracing till
nth scan cell, chain tracing was blocked due the
BLACK BOX present in the scan chain path
and reports T3 violation by tool.
 This can be solved by loading the BLACK
BOX definition during the setup phase, which
will help the tool to trace the chain
from scan_out pin to scan_in pin
Case II :
 There is a trace blockage in scan chain at 2nd cell as there is no toggling activity of clock.
 When we trace back the clock pin, we can see that clock is coming from a mux and select line for mux is x.

 add_clock 0 clk1
add_input_constraint D –c0

 We also need to modify the test procedure to pulse the clk1.

Template gen_tp =
offstate “clk1” 0 ;
force_pi 0 ;
 measure_po  100 ;
pulse clk1 200 100 ;
period 400 ;
end;
procedure test_setup =
temeplate gen_tp ;
cycle =
force D 0 ;
pulse clk1 ;
end ;
end;
Test Patterns :

 WGL – Waveform Generation Language

 STIL – Standard Test Interface Language
 ASCII – American Standard Code for Information Interchange
 Verilog Testbenches

Need to save patterns in the above format for simulation purpose

ATPG Observations:

 Coverage Analysis
 Pattern Count
 Cycle Count
 Types of Patterns
 Statistical Reports
 Fault List
THANK
YOU