DESIGN FOR TESTABILITY (DFT)

CHAPTER 2:

1. Explain about Simulation for Design Verification?

A.) Simulation serves two distinct purposes in electronic design. First,
it is used to verify the correctness of the design and second, it verifies
the tests. The first form of simulation is illustrated in Figure

Specification: The process of realizing an electronic system begins with

its specification, which describes the input/output electrical
behavior(logical, analog, and timing) and other characteristics (physical,
environmental, etc.)
The specification, shown as a shaded block in the figure, is the starting
point for the
design activity.
True value simulator: The process of synthesis produces an interconnect
of components (called a netlist.) The design is verified by a true-value
simulator. True-value means that the simulator will compute the
response for given input stimuli without injecting any faults in the
design.

Input Stimuli: The input stimuli are also based on the specification
Typically, these stimuli correspond to those input and output
specifications that are either critical or considered risky by the synthesis
procedures. A frequently used strategy is to exercise all functions with
only critical data patterns.

Computed response and its analysis: The true-value simulator in Figure

5.1 computes the responses that a circuit (if built using the netlist) would
have produced if the given input stimuli were applied.
In a typical design verification scenario, the computed responses are
analyzed (either automatically, or interactively, or manually) to verify
that the designed netlist performs according to the specification. If errors
are found, suitable changes are made, until responses to all stimuli match
the specification.

Advantages:
1. Its strength lies in the details of the circuit behavior that can be simulated.
For example, logic, timing, and analog behaviors can be simulated.
2.Another advantage is in the use of hierarchy. For example, a design
can be first simulated at a higher behavior level.

Disadvantages:
1. The weakness of this method is its dependence on the designer’s heuristics
used in generating the input stimuli. To contain the complexity, these stimuli are
non exhaustive and, therefore, a guarantee of conformance to specification is
impossible.
Such a guarantee is possible with a formal verification method , which
mathematically proves the correctness of the design. A restricted form of formal
verification,known as model checking verifies finite state concurrent systems by an
exhaustive search of the state-space.

2. Explain about Test Evaluation?

A. Another type of simulator, known as a fault simulator, is used for the
development of manufacturing tests. The fault simulator performs two functions:
1. It determines the coverage of a given set of input stimuli (vectors) for a given
fault model or a given fault list.
2. With the help of other programs it can produce a set of vectors with a given
fault coverage for manufacturing test.

It then simulates the initially supplied verification vectors. Simulation produces

lists of faults, detected by each vector. The detected faults are deleted from the
fault list. Fault coverage, defined as the ratio of the number of detected faults to
that of faults in the initial fault
list, is computed. Once an adequately high fault coverage (98-100%) is reached,
the simulation may be stopped. If there are unsimulated vectors, they can be
removed to reduce the vector set. On the other hand, if the vectors do not produce
an adequate fault coverage, some of the undetected faults from the fault list can be
given to a test generator program to produce new vectors.

Example 5.4 Fault simulation: Consider a four-bit ripple-carry adder circuit of

the type shown in Figure 5.2. This circuit contains four full-adder blocks of Figure
5.2(a.) It has 36 logic gates, 9 primary inputs, and 5 primary outputs. A fault
simulator [160] makes a list of 186 single stuck-at faults. The equivalence fault
collapsing option in the smulator reduces it to 114 faults. The result of fault
simulation with vectors of Table 5.1 is shown in Table 5.2. We make several
observations:
• The last vector does not detect any new fault. We can use the first six vectors for
testing the circuit without any reduction in the fault coverage. Even though the last
two vectors were necessary for the design verification heuristic of the last section,
they are found to be redundant for testing. For large circuits, it is not unusual to
have several million vectors in the verification vector set. A fault simulator can
significantly reduce the size of the vector set, thus reducing the time required for
the manufacturing test.
• The collapsed fault set is about 40% smaller than the set of all faults. A 40-50%
reduction in the fault list is quite typical.
• Although the coverages of collapsed and uncollapsed fault lists differ, they are
quite close. The CPU time for simulation of all faults on a SUN Sparc 2
computer was 33 ms, and reduced to 16 ms for the collapsed fault set. For
large circuits, the saving in the CPU time may be significant
Example 5.5 Reverse-order simulation: In the previous example, we found that the
last two vectors can be dropped without reducing the fault coverage Note that
vector 6 is essential since it detects some faults
that could not be detected by all 5 previous vectors. It is, however, possible that
vector 6 could detect faults covered by some previous vectors, making those
vectors unnecessary. This could not be determined earlier because of “fault
dropping” by the simulator. We can now use four vectors
above the line in this table for a 100% coverage. Unfortunately, the reverse-order
simulation cannot be used for sequential circuits..
3. What are different levels of Modeling and types of Simulators?
A.
 4.) Discuss Algorithms for True-value Simulation
A.) compiled code simulation:
In this method of simulation the circuit is described in a language that can be
compiled and executed on a computer. Levelization ascertains that the evaluation
of a signal is preceded by the evaluations of its sources. In circuits with feedback,
global levelization may not be possible. Compiled-code simulators are very
effective where two-state (0,1) simulation
suffices. Otherwise, the larger number of signal states makes the code complex.
The two-state simulation is useful for combinational logic and for sequential logic
which is already initialized. Another scenario is the high-level design verification
where the circuit is described using functional modules and stimuli are generated
by testbenches. Because the code execution can be very fast on a computer, such
simulators are capable of high speed.
Large gate-level circuits present several problems. First, timing problems –
glitches, race conditions, etc. – are not modeled in a compiled-code simulator In
digital circuits, generally only 1-10% of signals are found to change at any time.
For this reason, event-driven simulators run much faster at the gate-level. Finally,
any detailed timing (such as multiple-delay or minmax-delay) is almost impossible
to simulate in the compiled-code. For these reasons, the use of compiled-code
simulators is usually limited to high-level design verification

Step 1: Levelize combinational logic

and encode in a compilable
programming language
Step 2: Initialize internal state variables
(flip-flops)
Step 3: For each input vector
Set primary input variables
Repeat (until steady-state or max.
iterations)
Execute compiled code
Event driven simulation: Event-driven simulation [683, 684] is a very effective
procedure for discrete-eventsimulation. An event-driven simulator follows the path
of events. Consider a circuit at the gate-level. Suppose, all signals are in steady-
state when a new vector is applied to primary inputs. Some inputs change, causing
events on those input signals. Gates whose inputs now have events are called
active and are placed in an activity list. The simulation proceeds by removing a
gate from the activity list and evaluating it to determine whether its output has an
event. A changing output makes all fanout gates active, which are then added to
the activity list. The process of evaluation stops when the activity list becomes
empty.
An event-driven simulator only does the necessary. However, the biggest
advantage of this technique is in its ability to simulate any arbitrary delays. This is
done by a procedure known as event scheduling.

Figure 5.12: An example of event-driven simulation

5.) Explain about timing models of NAND gate.
a.)

In an electronic circuit, electrical parameters such as voltage and current are used
to encode the information being processed. Thus, in a digital system, a high
6.)Explain Roth’s test detect algorithm
A’)

Roth devised an easy-to-program algorithm for simulating faults in combinational

circuits. All gates are assumed to have zero delay. The circuit is simulated for a
vector in the true-value mode. This determines the states of all lines. Next, faults
are analyzed one at a time to determine which faults are detected by the presently
simulated vector. The analysis is based on Roth’s D-calculus that allows a
composite representation of a signal in the fault-free and faulty circuits. Assuming
a two-value simulation, the signal state (fault-free value, faulty value) can take four
8.)Explain about serial fault sampling
a.) Algorithms for Fault Simulation
 Purposesof fault simulation during design cycle:
 Guiding the TPG process.
 Measuring the effectiveness of the test patterns.
 Generating fault dictionaries.

 
 Faultsimulator needs in addition to the circuit
model, stimuli and expected responses (that are
needed for true-value simulation):
 Fault model
 Fault list
  C(f1)...C(fn) are copies of the defect-free circuit C( ) with fault fx
permanently inserted.
 
 Here, each time the fault is detected, the
simulator records the vector number (and
possibly the output(s) in error).
o Although useful for fault diagnosis,
this is compute expensive.
o Fault dropping causes simulation of
C(fn) to stop after vector 35.
Serial Fault Simulation
 If fault dropping is not employed, the effort of
simulating n faults is equivalent to either:
 Simulating a circuit n times larger or
 Repeating the original true-value simulation n times.

 
 
 Serial Fault Simulation
o True-value simulation is performed
across all vectors and outputs saved.
o Faulty circuits are simulated one-
by-one by modifying circuit and
running true-value simulator.
o Simulation of faulty circuit stops as
soon as fault is detected.
 
 Adv:
o Any type of fault can be simulated,
e.g., stuck-at, stuck-open, bridges,
delay and analog faults.
 
 For n faults, CPU time can be almost n times
that of a true-value simulator.
o Fault dropping significantly
improves on this.
8.) Explain about parallel fault simulation 
Parallel Fault Simulation
 Most effective when:
 Circuit consists of only logic gates.
 Stuck-at faults are modeled.
 Signals assume only binary, 0 or 1, values.
 All gates have the same delay (zero or unit).

 
  Under these conditions, circuits C(fn) are almost identical.
 
 Here, the bit-parallelism of logical
operations in a computer can be useful.
 For a 32-bit word, 1 fault-free and 31 faulty
circuits can be simultaneously simulated.
 
 This yields a speed up of w - 1, with w equal
to the word size.
o If fault dropping is employed,
simulation stops when all w - 1 faults
are detected.
 
o Therefore, serial fault simulation
has more to gain by fault dropping.
Parallel Fault Simulation
 Parallel fault simulation of two faults, c SA0 and f SA1:

 Parallel fault simulation cannot accurately model rise and fall delays.
o The signal values in all circuits are
processed simultaneously.
o Zero-delay or unit-delay are used.
 
 Compiled-code or event-driven versions are
possible.
o Multi-valued logic is possible, e.g.,
(0, 1, X and Z), by encoding state in
more than 1 bit.
 
 A true-value logic simulator can be used as a
parallel fault simulator by inserting gates to
model faults -- see text.
Parallel Fault Simulation

 Reduction possible:  f  SA1 eq  g SA0,  f SA1  dom b SA1

and  u SA0  dom g SA0.

  ff a/0 b/1 c/1 d/0 e/1 f/0 f/1 g/0 g/1 h/0 h/1 i/0 i/1 u/0 u/1
a=1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
b=0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
c=0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
d=1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
f=ab 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
g=f+c 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1
h=cd 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0
e=0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
 i=e+h 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0
u=g+h 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1

9.) Explain about deductive fault simulation

 A.) Circuit model assumptions are the same as those given for the
parallel fault simulator, compiled-code and event-driven versions possible.
 
 Only the fault free circuit, C( ), is simulated.
o Faulty circuit values are deduced from the fault-free
values.
 
o It processes all faults in a single
pass of true-value simulation, i.e., it
very fast!
 
 Note, however, that major modifications are
required (and slow downs) to handle variable
rise/fall delays, multiple signal states, etc.
 
 A vector is simulated in true-value mode.
o A deductive procedure is then
performed on all lines in level-order
from inputs to outputs.
 
 o Fault lists are generated for each
signal using the fault lists on the inputs
to the gate generating that signal.
Deductive Fault Simulation
 The fault list of a signal contains the names of all faults in the circuit that
can change the state of that line.

 Rules for fault list propagation:

Inputs Output Output fault list
Gate type
a b c Lc
0 0 0 [La intersection Lb] union c1
0 1 0 [La intersection Lb] union c1
AND
1 0 0 [La intersection Lb] union c1
1 1 1 [La union Lb] union c0
0 0 0 [La union Lb] union c1
0 1 1 [La intersection Lb] union c0
OR
1 0 1 [La intersection Lb] union c0
1 1 1 [La intersection Lb] union c0
0 - 1 La union c0
NOT
1 - 0 La union c1
Deductive Fault Simulation
 For example, if both inputs to a 2-input AND
are 0, in order for a fault to propagate through, it
must be in the lists of both inputs.
  True-value simulation is run first.

 Fault list for e is composed from the union of

the input lists for a and c, since the input is ab =
(11).
 Fault list for g is given by the intersection of
e's list and !f's list.
Deductive Fault Simulation
 Another example:

 With  ab = 10, only  L b is sensitizable to  f (faults on  a are masked).
o The faults given by

 are the faults in

 L b that are not in  L a union [ f 1]. Therefore,  L f = [ b 1,  f 1].

 
o Had  b = 1,  L a would have been sensitized to  f , e.g.,

10.) Explain about concurrent fault simulation

A.) Concurrent Fault Simulation
 It extends the event-driven simulation method to
simulation of faults.
o It can handle various types of circuit
models, faults, signal states and timing
models.
 
 Details of the simulator model:
 Events
o Good events: Occur in the fault-free
circuit, C( ), and have three attributes,
signal name, type of transition (0-to-1)
and time of change.
o Fault-events: Occur on same lines in
faulty circuits, C(f1)...C(fn), but ONLY
if transition is different from C( )
transition. Three attributes + fault site
and type.
 
 Circuit
o Modeled in the same way as for
true-value simulation.
 o Each good-gate has a fault list of
bad-gates associated with it.
Bad-gates are not faulty but
rather have an I/O that is
affected by some fault.
Concurrent Fault Simulation
 Faults
o Whenever the signal values of a
good-gate make a fault active, a bad-
gate is inserted into the fault list on that
good-gate.
 
 Event-driven simulation is carried out.
o Good-events and fault-events make
good-gates active for evaluation.
o Good-events also make bad-gates
active for evaluation.

Concurrent Fault Simulation

  This agrees with the deductive fault
simulator results.
o Note that deductive list is smaller --
fault lists include faults that affect a
signal line.
o In contrast, concurrent list contains
faults that affect the gate and includes
those that affect its inputs (adv in
memory, RTL and behavioral models).

 Note that we did not drop a0, c0, e0 and g0

after the first simulation for illustration only.
Concurrent Fault Simulation
 Second pass processes the activation of fault
a1 under the good-event transition
  The most significant advantages of this
algorithm are:
 Efficiency -- redundant computation is eliminated.
 Modeling flexibility -- anything that can be simulated.

 
11.) Explain about differential fault simulation
 A.) Cheng
and Yu made 2 improvements on
TEST-DETECT.
 Eliminated the use of D-calculus.
 Eliminated the explicit restoration to true-value before processing the next
fault.

 
 The algorithm, which starts with a vector set
and a fault list:
 Simulate a vector in true-value mode and store the PO values.
 Activate a fault by creating a transition to the faulty value, e.g., if true-value is
0 and it is a SA1, generate a 0 -> 1 transition.
 Simulate the circuit and check for a difference at POs -- drop the fault if
detected.
 For next fault, restore to true value by placing a restoring transition at previous
site. Place a second transition at new fault site and simulate.
 Repeat with the next vector once all faults have been analyzed.
 Figure 5.23: Differential fault simulation example: first vector (1,1).

Figure 5.24: Differential fault simulation example: second vector (1,0).

Figure 5.25: Differential fault simulation example: third vector (0,1).

Example 5.13 Fault simulation of a synchronous sequential circuit: Consider the

simulation of two faults shown as (1) and (2) in Figure 5.23. The vector set contains
three vectors, the first of which is simulated in Figure 5.23. The initial state of the
flip-flop is assumed to be unknown and is denoted as X. Both current and next
fault lists are empty. The fault-free circuit states indicate that none of the faults is
activated. After simulating the second vector (1,0) in Figure 5.24, we find that both
faults are activated. The effects of fault (1) are denoted as D(1) and those of fault
(2), as D2 Only D(l) reaches the flip-flop input and is added to the next fault
list. No fault is detected. Figure 5.25 shows the simulation of the third vector (0,1.)
The current fault list is updated with D (l), which now propagates to the primary
output. Thus, fault (1) is detected. No new fault effect is produced by this vector.
Since no fault effect is propagated to the flip-flop, the next fault list is now empty.
At this point, fault (1) can be dropped, and subsequent vectors will only simulate
fault (2), until that is detected too.

12.) Explain why the reverse-order fault simulation is not a practical test compaction
technique for sequential circuits.
A.)
Fault simulation: Consider a four-bit ripple-carry adder circuit of
the type shown in Figure 5.2. This circuit contains four full-adder blocks of Figure
5.2(a.) It has 36 logic gates, 9 primary inputs, and 5 primary outputs. A fault
simulator [160] makes a list of 186 single stuck-at faults. The equivalence fault
collapsing (see Chapter 4) option in the simulator reduces it to 114 faults. The
result of fault simulation with vectors of Table 5.1 is shown in Table 5.2. We make
several observations:
• The last vector does not detect any new fault. We can use the first six vectors for
testing the circuit without any reduction in the fault coverage. Even though the last
two vectors were necessary for the design verification heuristic of the last section,
they are found to be redundant for testing. For large circuits, it is not unusual to
have several million vectors in the verification vector set. A fault simulator can
significantly reduce the size of the vector set, thus reducing the time required for
the manufacturing test.
• The collapsed fault set is about 40% smaller than the set of all faults. A 40-50%
reduction in the fault list is quite typical.
• Although the coverages of collapsed and uncollapsed fault lists differ, they are
quite close. The CPU time for simulation of all faults on a SUN Sparc 2
computer was 33 ms, and reduced to 16 ms for the collapsed fault set. For
large circuits, the saving in the CPU time may be significant.
Note that vector 6 is essential since it detects some faults that could not be detected by all 5
previous vectors. It is, however, possible that vector 6 could detect faults covered by some
previous vectors, making those vectors unnecessary. This could not be determined earlier
because of “fault dropping” by the simulator. That is, a fault detected by a vector is immediately
dropped from consideration and is not simulated for the following vectors. So, we will simulate
vector 6 first. Similarly, we can argue that vector 5 could also detect faults covered by some
earlier vectors. A simple way to find that out is to simulate the vectors in the reverse order. The
result is shown in Table 5.3. We can now use four vectors above the line in this table for a 100%
coverage. Unfortunately, the reverse-order simulation cannot be used for sequential circuits.
13.) Explain what action an event-driven true-value simulator will take when it evaluates
a zero-delay gate?
A.)