AppNote 10050

Sharing EDT clock with scan clock in

TestKompress

By: Jayant D’Souza

Last Modified: March 10, 2008

Copyright © 1995-2007 Mentor Graphics Corporation.

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Table Of Contents:
Introduction .................................................................................................................................................... 2
Overview of TestKompress Pins .................................................................................................................... 2
Description of EDT pins............................................................................................................................. 2
Pattern generation using TestKompress ......................................................................................................... 3
Implementation Details .................................................................................................................................. 4
Scenario 1: Off-state of scan clock is 0 ...................................................................................................... 4
Scenario 2: Off-state of scan clock is 1 ...................................................................................................... 7
Conclusion.................................................................................................................................................... 10

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Abstract
This application note details how a user can share EDT clock with another clock pin for the purpose of
reducing the requirement of having a dedicated clock when using TestKompress. This approach is one
possible implementation of clock sharing logic to enable sharing a scan clock with EDT clock in
TestKompress ATPG.

Introduction
TestKompress is an automatic test pattern generator (ATPG) and is the industry standard for test
compression. It also provides the highest amount of compression of test data volume and test time with the
smallest pin overhead. TestKompress typically requires up to 5 pins. Most of these pins can be shared with
functional design pins. There are some restrictions, however, on how these pins are shared. One such
restriction is the sharing of EDT clock with another clock in the design. EDT clock, however, can be shared
with a non-clock pin in the design.
This appnote details one possible implementation to share EDT clock with another clock, such as the scan
clock, in the design. This alleviates the requirement of having an additional clock for EDT hardware.

Overview of TestKompress Pins

Figure 1: Overview of TestKompress Pins

The above figure shows the generic pin requirements for TestKompress.

Description of EDT pins

The EDT hardware includes the following pins:

1. Scan channel input pins – These pins form the input interface from the ATE to the design.
2. Scan channel output pins – These pins form the interface between the design and the ATE.
3. EDT_clock –The EDT hardware uses the EDT clock to drive the shift register in the
decompressor.
4. EDT_update – The EDT update signal is used to reset/update the contents of the mask register
and the shift register in the decompressor.
5. EDT_bypass (optional) — The EDT_bypass pin is included when the user specifies bypass
circuitry.
6. EDT_reset (optional) — The EDT_reset pin is included when an asynchronous reset for the EDT
logic has been specified.

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Each of these pins can be shared with functional pins. The table below shows how these pins can be shared
and all the restrictions involved in sharing those pins.

Scan Channel inputs Can be shared.

Scan Channel outputs Should not be shared with core level bidi or tristate pins. Can be shared with Top-
level bidi and tristate pins. When shared, muxes will be inserted.

EDT_clock Can be shared with a non-clock pin. However, must be constrained when shared.
Sharing this pin will result in reduced test coverage.

EDT_update Can be shared with non-clock pin.

EDT_bypass Can be shared.

(optional)

Pattern generation using TestKompress

During the pattern generation phase, the following conditions must be satisfied in the EDT hardware to
ensure that the patterns generated are valid.
• During capture, edt_clock is not pulsed, preserving the contents of the EDT registers. This is done
to preserve the contents of the EDT registers.
• During the first cycle of the load_unload procedure, edt_clock is pulsed along with the assertion of
the edt_update signal. This is done to reset the decompressor and update the masking information
for the current pattern.

The figure below illustrates these conditions.

load_unload shift shift capture load_unload shift

scan_enable
Don’t Care

scan_clock

edt_update Don’t Care

edt_clock OFF

edt_bypass
Don’t Care

edt_reset
Figure 2: EDT signal waveform requirements

Notice that edt_clock must be at its OFF state during the capture cycle and must be pulsed during
load_unload cycle.

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Implementation Details
This section describes a possible implementation to enable the sharing of edt_clock with a regular
scan_clock. Since this is not the default behavior of the tool, small modifications to the dofile and test
procedure file are required. Specifically, the K5 DRC in TestKompress will check to see if all pins are
connected at the top level. Since the edt_clock pin does not exist, the default behavior of the tool is to issue
an error and stop. The following section details the modifications needed in the dofile and test procedure
file from IP creation phase to ensure pattern generation using TestKompress when edt_clock is shared with
scan_clock.

These are also discussed in this section. Using this method, a user can ensure that the conditions mentioned
in the previous are met.
There are two scenarios which are addressed here – when the off-state of the scan clock is 0 and when the
off-state of the scan clock is 1.
Scan clock can be driven from either the top level or through JTAG controller. EDT_update and
edt_clock_control is accessed directly from the top level. Scan enable may be used as edt_clock_control. In
this case, scan enable should be constrained to its off state in the capture cycle. This may lead to a loss of
test coverage.

Scenario 1: Off-state of scan clock is 0

Figure 3: Implementation when scan_clock signal has off state of 0

This implementation is as shown in Figure 3. In this case, when “edt_clock_control” is 0, the edt_clock
(“gated_edt_clock”) will also be in the off-state (or 0). Therefore, this pin must be constrained to 0 during
the capture cycle.

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The following changes are required in the dofile to enable this implementation:

set edt instances -edt_logic_top edt_i

set edt instances -decompressor edt_decompressor_i
set edt instances -compactor edt_compactor_i

add scan groups grp1 created_edt.testproc

add scan chains -internal chain1 grp1 /counter_i/edt_si1 /counter_i/edt_so1
add scan chains -internal chain2 grp1 /counter_i/edt_si2 /counter_i/edt_so2
add scan chains -internal chain3 grp1 /counter_i/edt_si3 /counter_i/edt_so3
add scan chains -internal chain4 grp1 /counter_i/edt_si4 /counter_i/edt_so4
add scan chains -internal chain5 grp1 /counter_i/edt_si5 /counter_i/edt_so5
add scan chains -internal chain6 grp1 /counter_i/edt_si6 /counter_i/edt_so6
add scan chains -internal chain7 grp1 /counter_i/edt_si7 /counter_i/edt_so7
add scan chains -internal chain8 grp1 /counter_i/edt_si8 /counter_i/edt_so8

add clocks 0 clock

add clocks 0 clear

//edt_clock does not exist at the top-level and hence should be removed from
//the clock definition
//add clocks 0 edt_clock
//edt_clock_control is constrained to ensure that edt_clock does not pulse
//during the capture cycle
add pin constraints edt_clock_control C0

// EDT settings. Please do not modify.

// Inconsistency between the EDT settings and the EDT logic may
// lead to DRC violations and invalid patterns.

set edt -channels 4 -bypass_logic on -ip_version 3 -decompressor_size 16 -

injectors_per_channel 2 -scan_chains 8

set edt pins update edt_update

set edt pins scan_en scan_en
set edt pins bypass edt_bypass

// To prevent the tool from giving a K5 error because EDT_clock is not found
set drc handling k5 warning
set system mode atpg
create patterns -auto

Figure 4: Dofile for implementation of scenario 1

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 The test procedure file must also be modified to enable this implementation. The text in bold are the
changes from the default TestKompress test procedure file.
set time scale 1.000000 ns ;
set strobe_window time 10 ;

timeplate gen_tp1 =
force_pi 0 ;
measure_po 10 ;
pulse clock 20 10;
// pulse edt_clock 20 10; // edt_clock does not exist at the top level
period 40 ;
end;

procedure shift =
scan_group grp1 ;
timeplate gen_tp1 ;
cycle =
force_sci ;
force edt_update 0 ;
force edt_clock_control 1; // Ensure that during shifting the edt clock
// (scan clock) is being pulsed
measure_sco ;
pulse clock ;
// pulse edt_clock ; // edt_clock does not exist at the top level
end;
end;

procedure load_unload =
scan_group grp1 ;
timeplate gen_tp1 ;
cycle =
force clear 0 ;
force clock 0 ;
force edt_bypass 0 ;
// force edt_clock 0 ; //edt_clock does not exist at the top level
force edt_update 1 ;
force scan_en 1 ;
// pulse edt_clock ;
end ;
cycle = // Make sure that edt_clock is going to be pulsed during scan shift
force edt_clock_control 1;
end;
apply shift 21;
cycle = // Make sure that edt_clock is OFF at the end of scan shift
force edt_clock_control 0; //
force edt_update 0; //
end; //
end;

Figure 5: Test procedure file for scenario 1 implementation

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 Figure 6: Waveforms for the scenario 1
Note that in the waveforms above, gated_edt_clock (which is generated from scan clock) is pulsed when
edt_update is high during scan load and is at its off-state (0) during the capture cycle.

The load cycle that occurs after scan shift is specifically added to ensure that the edt clock is at its off-state
during launch and capture.

Scenario 2: Off-state of scan clock is 1

Figure 7: Implementation when scan_clock signal has off state of 1

When the off-state of the scan clock is 1, the implementation is only slightly different from that when the
off state is 0 (see Figure 7). The dofile required for the implementation of this scenario is as shown in
Figure 8. The only change is the off state of the scan clock in the clock definition is 1.

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 set edt instances -edt_logic_top edt_i
set edt instances -decompressor edt_decompressor_i
set edt instances -compactor edt_compactor_i

add scan groups grp1 created_edt.testproc

add scan chains -internal chain1 grp1 /counter_i/edt_si1 /counter_i/edt_so1
add scan chains -internal chain2 grp1 /counter_i/edt_si2 /counter_i/edt_so2
add scan chains -internal chain3 grp1 /counter_i/edt_si3 /counter_i/edt_so3
add scan chains -internal chain4 grp1 /counter_i/edt_si4 /counter_i/edt_so4
add scan chains -internal chain5 grp1 /counter_i/edt_si5 /counter_i/edt_so5
add scan chains -internal chain6 grp1 /counter_i/edt_si6 /counter_i/edt_so6
add scan chains -internal chain7 grp1 /counter_i/edt_si7 /counter_i/edt_so7
add scan chains -internal chain8 grp1 /counter_i/edt_si8 /counter_i/edt_so8

add clocks 1 clock

add clocks 0 clear

//edt_clock does not exist at the top-level and hence should be removed
//from the clock definition
//add clocks 0 edt_clock
//edt_clock_control is constrained to ensure that edt_clock does not pulse
during the capture cycle
add pin constraints edt_clock_control C0

// EDT settings. Please do not modify.

// Inconsistency between the EDT settings and the EDT logic may
// lead to DRC violations and invalid patterns.

set edt -channels 4 -bypass_logic on -ip_version 3 -decompressor_size 16 -

injectors_per_channel 2 -scan_chains 8

set edt pins update edt_update

set edt pins scan_en scan_en
set edt pins bypass edt_bypass

// To prevent the tool from giving a K5 error because EDT_clock is not found
set drc handling k5 warning
set system mode atpg
create patterns -auto

Figure 8: Dofile for implementation of scenario 2

The test procedure file is as follows. The only difference in this implementation is that the scan clock is
forced to its off state of 1 during scan load.

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set time scale 1.000000 ns ;
set strobe_window time 10 ;

timeplate gen_tp1 =
force_pi 0 ;
measure_po 10 ;
pulse clock 20 10;
// pulse edt_clock 20 10; // edt_clock does not exist at the top level
period 40 ;
end;

procedure shift =
scan_group grp1 ;
timeplate gen_tp1 ;
cycle =
force_sci ;
force edt_update 0 ;
force edt_clock_control 1; // Ensure that during shifting the edt clock
// (scan clock) is being pulsed
measure_sco ;
pulse clock ;
// pulse edt_clock ; // edt_clock does not exist at the top level
end;
end;

procedure load_unload =
scan_group grp1 ;
timeplate gen_tp1 ;
cycle =
force clear 0 ;
force clock 1 ;
force edt_bypass 0 ;
// force edt_clock 0 ; //edt_clock does not exist at the top level
force edt_update 1 ;
force scan_en 1 ;
// pulse edt_clock ;
end ;
cycle = // Make sure that edt_clock is going to be pulsed during scan shift
force edt_clock_control 1;
end;
apply shift 21;
cycle = // Make sure that edt_clock is OFF at the end of scan shift
force edt_clock_control 0; //
force edt_update 0; //
end; //
end;

Figure 9: Test procedure file for implementation of scenario 2

Note that in the waveforms below, gated_edt_clock (which is generated from scan clock) is pulsed when
edt_update is high during scan load and is at its off-state(1) during the capture cycle.
The load cycle that occurs after scan shift is specifically added to ensure that the edt clock is at its off-state
during launch and capture.

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 Figure 10: Waveforms for scenario 2

Conclusion
This implementation will enable reuse of the scan clock as edt clock, thereby reducing the requirement of
having a dedicated edt clock pin. The edt clock control pin and the edt update pin need to be at the top level
and can be shared with functional pins but test coverage could be lost due to constraints on those pins.

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