Weekly Assessment

ASIC Design Flow

And
IC Packaging
Presented by:
Apoorva

Jigar Kumar Luhar

 CONTENTS
❑ ASIC Design Flow
❑ IC Packaging
❑ WorkDone

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ASIC Design Flow

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 Chip Specification

❑ It defines features, microarchitecture, functionalities (hardware/software

interface), specifications (Time, Area, Power, Speed) with design
guidelines of ASIC.

❑ Two different teams are involved at this juncture:

• Design team: Generates RTL code.
• Verification team: Generates test bench.

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 Functional Verification

❑ Functional verification confirms the functionality and logical behavior of

the circuit by simulation on a design entry level.

❑ This is the stage where the design team and verification team come into
the cycle where they generate RTL code using test-benches.

❑ This is known as behavioral simulation.

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 Functional Verification

❑ There are two types of simulation tools:

• Functional simulation tools:

• Timing simulation tools:

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 RTL Synthesis
❑ It is a process of converting the RTL code into gate level netlist.

❑ In synthesis process the design is converted into technology dependent.it is 3 stage

process.

1.Translation

2.Optimization

3.Mapping

The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated
outputs are gate level netlist and .SDC.

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 Chip Partitioning
❑ Chip Partitioning is a process of dividing the chip into small blocks.

❑ This is done mainly to separate different functional blocks and also to

make placement and routing easier.

❑ These modules are linked together in the main module called the TOP
LEVEL module.

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 Design for Test (DFT)
❑ Design for testability(DFT) is a technique which facilitates a design to
become testable after production.

❑ In this stage we put extra logic along with the design logic during
implementation process which helps post production process.

❑ The DFT will make the testing easy at post production process.At this
stage an ATPG(automatic test pattern generator) file will generated.

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 Design for Test (DFT)
❑ In order to overcome this situation, design for test is introduced with a list
of techniques:

❑ Scan path insertion

❑ Memory BIST (built-in Self-Test)

❑ ATPG (automatic test pattern generation)

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 Floor Planning

❑ After, DFT, the physical implementation process is to be followed. In

physical design, the first step in RTL-to-GDSII design is floorplanning.

❑ It is the process of placing blocks in the chip.

❑ It includes:
1. Block placement
2. Design portioning
3. Pin placement
4. Power optimization.

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 Inputs for floorplan
❑ Netlist (.v)
❑ Technology file (techlef)
❑ Timing Library files (.lib)
❑ Physical library (.lef)
❑ Synopsys design constraints (.sdc)
❑ Tlu+

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 Placement

❑ Placement is the process of finding a suitable physical location for each

cell in the block.

❑ A poor placement requires larger area and also degrades performance.

❑ Various factors, like the timing requirement, the net lengths and hence
the connections of cells, power dissipation should be taken care.

❑ It removes timing violation.

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 Inputs and output of placement:
Inputs
❑ Netlist
❑ Floorplan def
❑ Logical and physical library
❑ Design constraint
❑ Technology file

Output:
❑ Placement def

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 Clock Tree Synthesis
❑ Clock tree synthesis is a process of building the clock tree and meeting
the defined timing, area and power requirements.

❑ It helps in providing the clock connection to the clock pin of a sequential

element in the required time and area, with low power consumption.

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 Clock Tree Synthesis
❑ With the help of these structures, each flop in the clock tree gets the
clock connection.

❑ During the optimization, tools insert the buffer to build the CTS
structure.

❑ Different clock structures will build the clock tree with a minimum buffer
insertion and lower power consumption of chips.

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 Inputs required for CTS
❑ Placement def
❑ Target latency and skew if specify (SDC)
❑ Buffer or inverters for building the clock tree
❑ The source of clock and all the sinks where the clock is going to feed
Clock tree DRC (max Tran, max cap, max fan-out, max no. of buffer
levels)
❑ NDR (Nondefault routing) rules (because clock nets are more prone to
cross-talk effect)
❑ Routing metal layers used for clocks.

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 Output of CTS
❑ CTS def
❑ Latency and skew report
❑ Clock structure report
❑ Timing Qor report

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 Routing
Routing is the process of creating physical connections based on logical
connectivity. Signal pins are connected by routing metal interconnects.
Routed metal paths must meet timing, clock skew, max trans/cap
requirements and also physical DRC requirements.

There are four steps of routing operations:

1. Global routing
2. Track assignment
3. Detail routing
4. Search and repair

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 Final Verification
❑ After routing, ASIC design layout undergoes three steps of physical
verification, known as signoff checks. This stage helps to check whether
the layout working the way it was designed to:

1. Layout versus schematic(LVS)

2. Design rule checks(DRC)

3. Logical equivalence checks(LVC)

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GDS II- Graphical Data Stream Information Interchange
❑ In the last stage of the tapeout, the engineer performs wafer processing,
packaging, testing, verification and delivery to the physical IC.

❑ GDSII is the file produced and used by the semiconductor foundries to

fabricate the silicon and handled to client.

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INTEGRATED CIRCUIT PACKAGING

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 IC Packaging-Introduction
❑ IC packaging refers to the material that contains a semiconductor
device.
❑ The package is a case that surrounds the circuit material to protect it
from corrosion or physical damage and to allow for mounting of the
electrical contacts connecting it to the PCB.
❑ Different types of integrated circuits, and therefore there are different
types of IC packaging to consider.

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 Types of IC Packaging
1. Dual In-line Packages [DIP], or Dual In-Line [DIL] packages are packages
with two rows of leads on two sides of the package. DIP ICs may be
through-hole [PDIP or CERDIP] or SMT package [SOJ or SOIC].
2. Quad Flat Packs or Chip Carriers are square packages [or nearly
square], with leads on all four sides. Examples :PLCCs and other
variants are strictly Surface Mount Technology (SMT).
3. Grid Arrays are those type of packages that have their pins arranged in
a grid. The pin grid may consist of Leads, pads, or solder balls on an
area array.

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 Mounting Style
1. Through-hole packages are generally bigger, and much easier to work
with. They’re designed to be stuck through one side of a board and
soldered to the other side.
2. Surface-mount packages range in size from small to minuscule. They
are all designed to sit on one side of a circuit board and be soldered to
the surface.

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 Surface Mount Package Types
❑ BGA - Ball Grid Array
• Very common for high volume high-pin-count chips
• Packaging technique developed by IBM. BGA is type of surface mount
packaging.

• Advantages include high package density , better heat conduction, low

inductance.

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❑ SOP - Small Outline package
• SOP package is a lead frame based package with gull-wing type leads,
which are drawn out from the two sides of the package body.
• It includes large family of packages like SOIC, SSOP,QSOP.
• SOIC packages are the surface-mount cousin of the DIP.

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❑ QFP - Quad Flap Package
• Oldest Surface mount packages , used mainly on military programs
• QFP package is a flat structure with 4-sided peripheral leads which
provides medium high pin counts.
• Used for SRAM, graphic processors, PC Chipsets, digital signal
processors, multi-media and other related devices.

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❑ SOJ – Small Outline J-lead
• Small outline package with J leads on both sides. The leads are bent
back around the chip carrier. Easy to solder by hand, infrared and reflow
techniques. Commonly used for crystal oscillators.

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 Work Done
1. Apoorva
❑ Placement and its steps
❑ Physical design flow
❑ Research paper : “STRATEGIES & METHODOLOGIES FOR LOW
POWER VLSI DESIGNS” Kanika Kaur and Arti Noor at International
Journal of Advances in Engineering & Technology, May 2011.

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 Work Done
2. Jigar
❑ ASIC Design Flow
❑ Research Paper: M. Shunmugathammal, C. Christopher Columbus And
S. Anand “A SURVEY: ON VARIOUS PLACERS USED IN VLSI STANDARD
CELL PLACEMENT AND MIXED CELL PLACEMENT” Int. J. Chem. Sci.:
14(1), 2016,ISSN 0972-768X

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 Work Done
3. Susmita Bera
❑ ASIC Flow
❑ IC Packaging Basics
❑ Research Paper: Ganesh Prasad J, Sudha R Karbari, Sajees A, Sukanya K
Bellal “Analysis, Physical Design and Power Optimization of Design
Block at Lower Technology Node” 3rd IEEE International
Conference(RTEICT-2018)

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