Small things or grepping things we did to check the scan insertion:

 Got feedback from atpg saying T24 violation

Warning: A lockup latch may be required between
/inst_audio_ss_shell/inst_audio_ss/pd1_inst_u_audio_pd1_inst/u_dsp1_ss/dsp1_inst_u_dsp/Xt
ensa/TIE/TIE_State_AE_SAR/TIE_State_AE_SAR_bank0/ins_def4_C4/i0/tmp_reg_0 (2332115) of
cell 186 and
/inst_audio_ss_shell/inst_audio_ss/u_audio_pd0_inst/u_dsp0_ss/dsp0_inst_u_dsp/Xtensa/Exte
rnInt/writebuffer/FIFO/icore0/iword13/tmp_reg_104 (2280853) of cell 185 in scan chain
chain_mss_per_ss_edt0_389. (T24-906)
For few blocks lockup latch was missing in between the clk cross domains
To verify above thing we went for scan_path cell report and checked for the latch in between
the two clk cross domain for the corresponding cell.

If you see in above there is a latch in between , this is correct so sometimes tool gives fake
violation

Similarly if you see above image, there is no lookup latch in between the clk crossing . so this we
checked and verified.

 Getting the data for clk and its driven flops count
Usually in intest (wrp_if) mode clk mixing was done so chain balancing was easy to do no.s of
flops by edt chains.
But in extest (wrp_of) mode clk mixing is ont allowed so clk flops should connected to one chain
so for some blocks extra port was generated of balancing was not possible so to get the number
of clk and flops of corresponding clk we took atpg scan_cell report and sorted with the clk
names and took the details of number of clk and flops connected to it.

wrap
core per
co inter wrap inter
re nal per nal
ar ed chai edt chai
block ch clock t ff ns ff ns
3b
-
bpss_pegas PI 33 152
us_part P gclk_pegasus_clk_pegasus0_lx7_core3 12 0 270 60
3b
-
bpss_pegas PI feedthrough_bpss_noc_part_va_to_bpss_pegasus_p 152
us_part P art_bpss_clk_sysm_monmux_i_i 8 0 6 60
 3b
-
bpss_pegas PI 46 152
us_part P gclk_pegasus_dtcm_mux_pegasus_lx7 0 0 74 60

 Reading the ctl chain and attaching it to the edt regular chain
We started reading the analog ip ctl to the design but tool was not able to read the ctl to its
corresponding analog ips present in the block
Below is the command used in the user_dft.tcl to read the ctl
set user_defined_ctl_list [list \
dft_wrapper_bandgap
/p/hdk/rtl/ip_releases/whdk/xg816/sip/dfx_collaterals_816/latest/common_dft_rtl/ana
log_dft_wrapper/ctl/dft_wrapper_bandgap.ctl ]

mistake we did in the above command we dint give correct module name of the analog ip so I
was not able to read and attach the ctl

*dft_wrapper_bandgap*
/p/hdk/rtl/ip_releases/whdk/xg816/sip/dfx_collaterals_816/latest/common_dft_rtl/ana
log_dft_wrapper/ctl/dft_wrapper_bandgap.ctl
ppu_top_dft_wrapper_ipn7mtgviewpin_0
/p/hdk/rtl/ip_releases/whdk/xg816/sip/dfx_collaterals_816/latest/common_dft_rtl/ana
log_dft_wrapper/ctl/dft_wrapper_ip731_viewpin.ctl

you can see for few module *module* worked and for few I went inside netlist to check the
module name and added into the tcl so it worked. using the instance name we searched for its
module.
Since analog ctl was having only one chain with pulse_enable_reg and shift regs. Only pulse
enable need to be added in the chain so we intimated to make two chains.
 Above if you see si and so will be connected to the edt regular since from si to so we see both
pulse enable and shift reg. we dint use this ctl.
And in few ctl there some mismatch in the ports and port numbers so tool was not attaching
those ctl to the design.

 Calculating the edt compression ratio for blocks

Below table gives formula and calculation of compression ratio

 Checks done in check.pl

Block name, architecture,
 Version of scan_synthesis_proc/scan_exclusion
Edt/ltcu preservation
Any errors in log
D1/d2/d3/d4 violations
Pre scannability no.
X propogation
Ltest_to_reset/srcm in scan cells
TEST-352
Extra ports
Wrp_if & of s1/s2/s3/s19/s22
Max length of regular chain/wrp _if/of_input/wrp_if/of_ouput
‘No clock’ presence status
Bisr/ltcu not present in scan cells
Scan exclusion cell/instance count from compile.log
 In extract_scan_reports_816.pl

Other than DRC check done in above script(except highlighted) many info is present as below

No of Sequential_cells/ non scan elements/

No of Core_segments/core segment cells/ violated core segments/core segments without
violation/ excluded core segments
Lockup latch count
Self gate, no of ltest/sib sti in design
Cscc hooked to 0th chain of EDT/length of scc
No of srcm in design/srcm registers/sasc registers/dtcm registers
Presence of wrp_if/wrp_of , expectation of wrp_if/of
Arch 1 and 2a regular chain min and max length/flop count
Intest chain trace status-cscc/edt regular/wrp_if_input/wrp_if_output
cscc chain/regular chain/wrp_if_input/wrp_if_output min and max length and flop count
Extest cscc chain/wrp_of_input/wrp_of_output trace status
cscc chain/wrp_of_input/wrp_of_output min and max length and flop count
core edt chain available/chain length/chains required for 300 ff/edt redo required or not
wrapper edt chain available/wrapper flop count/in wrp chain req/out wrp chain req
in and out chains generated in SD/total chains
no of input port/output port
shared/dedicated input and output flop, post nonscan elements.

 Non scan analysis for atpg non scan cell report

Total non scan cells are : 106

In that, icdg_scan excluded are : 84

Latches are :0
Due to D1,D2 and D3 are : 22

 Edt redo for chain balance and remove extra ports

 T24 violation in atpg
T24 warnings are because there is no lockup latch in between the clock cross domain and the ctl
chain end
// Warning: A lockup latch may be required between
/\u_symproc_flex_proc/u_pegasus_dma_xbar_async_cross_wr_m
/\u_wr_intf_in_addr_fifo/u_dma_async_fifo_mem_ctech /u_dma_async_fifo/addrRgray_reg_2
(5037721) of cell 48 and /u_cscc_hap_clk_proc_fbr/u_cscc_hap/DIV_BY_X_obs_reg_reg
(4978866) of cell 47 in scan chain chain_flex_proc_symproc_edt0_302. (T24-1)

There should be on latch in between the two regs since the both clk names are difference.
So we check its clock pin in the block and we compared the two clk pins whether it getting clk
from common source , this we can do in iclock table where it has all details about clock.
If it is of same source then we will make it has fake violatioin.
If the source are difference , then we will should add one lockup in between in eco fix.

 F22 Violation in atpg

F22 violations are because of there is no terminal lockup latch in the starting and end of the
chain, because usually edt flops will be having edt clocks and the next when the chain starts
clock will change so commonly there will be termimanl lockup latch is required.

/ Warning: Two adjacent cells of scan chain 'chain_symproc_lx7_ss_edt0_729' and the

compactor are clocked on the same edge by different clocks.
//
'/u_symproc_lx7_wrapper/inst_symproc_cltrnoc/dtp_Link53_pwrDiscTarg_Link54/RspPwrClkAd
apt_Async/urs/Isc1/symproc_cltrnoc_sync_ff/doublesync_rstb/sync_reg_1_0/Q' (2723444),
driven by clock '/pin_symproclx7_clk_symproc_lx7_core0_HAP_CSCC' (2102), and
//
'/inst_symproc_lx7_ss_core_edt/symproc_lx7_ss_core_edt_compactor_i/compactor5/level8_pi
pelined_reg' (2906563), driven by clock '/edt_clock' (168).
// Consider adding a lockup cell between them, or modifying the clock timing. (F22-1)

Usually for cscc chain and all if you see inside the ctl itself there is a terminal lockup at the first
and last so when these chains are connected to the edt terminal lockup latch is not required. So
we can consider this as a fake violation.
If there is regular chains means this should be be fixed.