INTRODUCTION & TAP

CONTROLLER

BY
B BHARATH BHASKAR
  Introduction

• Testing a stand-alone chip is easy because all I/O pins are controllable and  observable
with external test equipment, but Once a chip is mounted on a  PCB, the problem
becomes more complex.
• The conventional way of testing by probing on-board test pins and vias has 
encountered difficulties and has been phased out.
• The group known as the Joint European Test Action Group (JETAG)  concluded  that the
best way to address this problem is to chain all the boundary I/O pins  of a chip into a
shift register and use a concept similar to scan design to gain  back the I/O accessibility
of the chip.
• Then with North American group they formed a group called Joint Test Action Group
(JTAG) and the idea of “boundary scan” was formally converted into a  test
architecture and a set of associated design rules, which were quickly  approved by the
IEEE as a test standard (Std. 1149.1) in 1990. This is now  used  widely.
  IEEE 1149 Standard Family-
• Standard 1149.1- defines only a general-purpose boundary scan  implementation for
digital chips, but for other purposes there were other standards released.
• Standard  1149.2 - was for application-specific integrated circuits (ASICs) and tried to
add high-speed boundary-scan test capability, while 1149.3 targeted the direct access
interface of a chip, emphasizing system testability specifications. 
• Standard 1149.4- defines the chip-level test architecture for circuits with analog  I/O,
now referred to as analog boundary scan.
• Standard 1149.5- approved in 1995, defines the test and maintenance bus  protocol at
the module level. 
• Standard 1149.6- approved by the IEEE in 2003, is an extension of 1149.1  designed to
standardize boundary scan for high-speed (1+ Gbps) I/O designs.
  TAP Controller & Ports
• The TAP controller (TAPC) is a 16-state, finite-state machine that operates according
to the state diagram shown in Figure 1. 
• The TAPC can change state only on the rising edge of TCK. The next state is
determined by the logic level of TMS. The output signals of the TAPC determine the
test operation to be carried out.
• main functions of the TAPC are:
1. Resetting the boundary-scan architecture. 
2. Providing control signals to load  instructions into the instruction register.
3. Providing signals to perform test functions such as Capture and
Update (application) of test data.
4. Providing control signals to shift test data from TDI to TDO.
• As shown in Figure 2, There are
nine control signals
• ClockDR 
• ShiftDR 
• UpdateDR 
• ClockIR
• ShiftIR 
• UpdateIR
• Select 
• TCK
• Enable—as well as Reset∗
(optional) are produced by the
TAPC.
• The 16 states can be divided into three
parts. 
• The first part (the 2 states at left)
contains the reset and the
“Run-Test/Idle” states, the second (the
7 states in the middle) and third (the 7
states at right) parts control the
operations of the data and instruction
registers, respectively.
• The only difference between the
second and the third parts is the
registers they deal with.
Pin Descriptions-
• Test–Logic–Reset—The test logic of the JTAG scan chain is disabled. 
• Run-Test/Idle—This is a hold state. Once entered, the controller remains in this state as long
as TMS is held low.
• Select-DR-Scan—These are temporary controller states. A decision is made here whether to enter
the DR states or the IR states.
• Capture-DR—These states enable a parallel load of the shift registers from the hold registers on
the rising edge of TCK.
• Shift-DR—In this state, test data are scanned in series through the data registers selected by
the current instruction. Upon entering this state, the TAP controller will stay in this state as long as
TMS = 0.
For each clock cycle, one bit of test data will be shifted into (out of) the selected data
register through TDI (TDO). 
• Exit-DR—Temporary hold states. A decision is made in these states to either advance to
the Update states or the Pause states.
• Pause-DR—The boundary-scan logic pauses its function here to wait for some external operations. 
• Exit2-DR—This state either indicates completion of the current capturing/shifting operation and
allows the TAPC to enter the update state or represents the end of the Pause-DR operation, allowing
the TAP controller to go back to the Shift-DR state for more data to shift in/out. 
• Update-DR—These states enable a parallel load of the hold registers from the shift registers. Update
happens on the falling edge of TCK.
 Instruction Register and Instruction Set 
• The instruction register is used to store the
instruction to be executed.
• Some of the Instruction set for above function
are-
1. BYPASS -The BYPASS instruction is used to
“bypass” the boundary-scan registers on
unused chips so as to prevent long Shift
operations as shown in fig.
• The BYPASS register must capture a default bit of
0 at the Capture-DR state when this instruction is
executed.
• By default the tap controller must be loaded with
bypass instruction.
3. PRELOAD—The PRELOAD instruction
allows test data to be shifted into or out of
the selected data register during the Shift-
DR state without causing interference to the
normal operation of the internal logic, as
shown in Figure.
• The shifted data are then latched to the
parallel output (R2) of the selected data
registers or immediate or later use.
• This allows an initial data pattern to be
placed at the latched parallel outputs
before the selection of other test
operations.
4. EXTEST—The EXTEST instruction is used to test the circuitry external to the chips, typically the
interconnects between chips and between boards.
• Assume that an interconnect line from Chip1 to Chip2 as shown is to be tested. 
• First, the test pattern is shifted into the “driving terminals” of Chip1 through its TDI pin during the
ShiftDR state of the TAP controller. 
• Second, an Update operation in Chip1 is executed on the falling edge of the TCK such that the shifted
test data bit is loaded to the corresponding output pin of Chip1.
• A Capture operation is then executed in Chip2 on the rising edge of the TCK and the test data bit is
captured at the driven terminal of Chip2 and then ShiftDR operation is executed in Chip2 and the
received test response can be scanned out through the TDO of Chip2 for examination. 
• The process is shown -
STEP-1

STEP-2

STEP-3

STEP-4
5. INTEST—Figure shows the steps of the INTEST instruction 
•  first step, test data are shifted into the boundary-scan cells
that drive internal logic. 
• the second step, an Update operation is executed and the
shifted data are loaded to the second stage of the boundary-
scan cell 
• at the same time the data are applied to the internal logic. 
• The TAP controller then goes back to the Capture-DR state to
capture the test result 
• Finally, the Shift-DR operation shifts the test results out for
observation. 
9. USERCODE—The USERCODE instruction
allows a user-programmable 32- bit
identification code to be loaded into the
user-defined device-ID register and then
shifted out for examination.
• This instruction is useful when the chip
can be programmed in various ways
and it is necessary to determine the
way in which the chip is programmed.
10. HIGHZ—When the HIGHZ instruction is
selected for a chip, all output pins of the
chip shall be placed in an inactive-drive
state. 
• This will allow an in-circuit system
tester to drive the chip outputs to
some desired state without damaging
the chip. 

 Optional/mandatory JTAG instructions-

Thank You