Clock generation, clock distribution, clocked storage

elements
 Clock
• Synchronous systems use a clock to distinguish one
step in a computation from the previous or next step.

• Ideally, this clock should arrive at all clocked

elements in the system simultaneously so that the
system shares a common time reference.
• These elements include latches and flip-flops,
memories, and dynamic gates.
• In practice, the arrival time differs somewhat from
one point to another; this difference is called clock
skew.
• The challenge in clock system design is to deliver the
clock to all the clocked elements on the chip while
finding compromise among skew, power
consumption, metal resource usage, and design
effort.
 On-Chip Clock Generation and Distribution
• Clock signals are the heartbeats of digital systems. Hence,
the stability of clock signals is highly important.
• Ideally, clock signals should have minimum rise and fall
times, specified duty cycles, and zero skew.
• In reality, clock signals have nonzero skews and
noticeable rise and fall times; duty cycles can also vary.
• A simple technique for on-chip generation of a primary
clock signal would be to use a ring oscillator as shown in
Fig.1. Such a clock circuit has been used in low-end
microprocessor chips.

Simple on-chip clock generation circuit using a ring oscillator

• However, the generated clock signal can be quite process-
dependent and unstable. As a result, separate clock chips which
use crystal oscillators have been used for high- performance VLSI
chip families.
• Figure.2 shows the circuit schematic of a Pierce crystal oscillator
with good frequency stability. This circuit is a series-resonant
circuit in which the crystal sees a low load impedance across its
terminals.
• Series resonance exists in the crystal but its internal series
resistance largely determines the oscillation frequency.
• In its equivalent circuit model, the crystal can be represented as a
series RLC circuit; thus, the higher the series resistance, the lower
the oscillation frequency.
• The external load at the terminals of the crystal also has a
considerable effect on the frequency and the frequency stability.
• The inverter across the crystal provides the necessary voltage
differential, and the external inverter provides the amplification to
drive clock loads.

Circuit diagram of a Pierce

crystal oscillator circuit
 Non-overlapping clock
signalsreceives one or more primary clock
Usually a VLSI chip
signals from an external clock chip and, in turn, generates
necessary derivatives for its internal use. It is often necessary
to use two non-overlapping clock signals. The logical product
of such two clock signals should be zero at all times. Figure .3
shows a simple circuit that generates CK-1 and CK-2 from the
original clock signal CK.

Figure-.3: A simple circuit that

generates a pair of non-
overlapping clock signals
from CK

Figure .4 shows a clock decoder circuit

that takes in the primary clock signals
and generates four phase signals.
 CLOCK DISTRIBUTION
• Since clock signals are required almost uniformly over the
chip area, it is desirable that all clock signals are distributed
with a uniform delay. An ideal distribution network would be
the H-tree structure shown in Fig. 5.
• In such a structure, the distances from the center to all branch
points are the same and hence, the signal delays would be the
same.
• However, this structure is difficult to implement in practice
due to routing constraints and different fanout requirements.
• A more practical approach for clock-signal distribution is to
route main clock signals to macroblocks and use local clock
decoders to carefully balance the delays under different
loading conditions.
Figure-.5: General layout
of an H-tree clock
distribution network.
• The reduction of clock skews, which are caused by the
differences in clock arrival times and changes in clock
waveforms due to variations in load conditions, is a
major concern in high-speed VLSI design.
• In addition to uniform clock distribution (H-tree)
networks and local skew balancing, a number of new
computer-aided design techniques have been developed
to automatically generate the layout of an optimum clock
distribution network with zero skew.
• Regardless of the exact geometry of the clock distribution
network, the clock signals must be buffered in multiple stages
as shown in Fig.7 to handle the high fan-out loads.
• It is also essential that every buffer stage drives the same
number of fan-out gates so that the clock delays are always
balanced.

Figure-7: Three-level buffered clock distibution

network.
 Phase Locked Loop Clock Techniques

clock clock
chip clock pad
chip
• PLL for synchronization PLL clock pad

clock route
clock route

dclk
dclk
output pad output pad
dclk +dpad dclk +dpad

clock clock
T1 T1=Input buffer delay
+routing RC delay dclk
dclk
T2 T2=Clock-to-Q delay T2
+output buffer delay
data out data out
 Phase Locked Loop – Clock Multiplying
Clock-multiplying PLL Synchronize data transfer between chips

clock

chip PLL clock pad

clock clock
/ clock route
4 PLL PLL
bus

dclk system clock

output pad
dclk +dpad Synchronize the output enable signals
1. Reduce tristate fights
2. Improve overall timing
clock

dclk
• Storage elements commonly used for the synchronization and
data storage in pipelines and other applications are
transparent latches and flip-flops. 
Latch
• Latch is a level-sensitive element with following functional
behavior: when control signal (clock) is at the active level, the
latch is transparent, i.e. the output follows any transition at the
input, Figure 1.
• When the clock is at the inactive level, the latch is opaque, i.e. it
holds the output state. The transition of the clock signal from
the active level to the inactive level is referred to as latching
edge, since the state of the output cannot be changed after this
edge.
• Similarly, we define the releasing edge of the clock as the
transition of the clock signal from the inactive level to the
active level.
• Depending on the values of the active and inactive level of the
control signal, a latch can be high-level transparent (when
active level is logical high) or low-level transparent (when
active level is logical low).
 The common configurations that use transparent latches are pulsed
latches and master-slave latches. 
Pulsed latch (PL) is a latch configuration in which a short pulse,
produced after one edge of the clock, is used as a clock input to the latch,
Figure 2.
In this arrangement, the latch is transparent only during a short time
after the active clock edge, while it is opaque otherwise, regardless of
the timing waveform of the clock.
In other words, the latch behaves as an edge-triggered storage element
(see flip-flop below).

Figure 2. Pulsed latch and timing diagrams

Figre 1. High-level transparent latch and timing diagrams

 Master slave latch (MS latch) is a particular arrangement of
transparent latches in which two latches are connected in
series and clocked with two independent clocks phases,
Figure 3.
• The input data D is captured at the latching edge of the
master clock and released to output Q at the releasing edge of
the slave clock.
• The timing parameters and the behavior of the master-slave
latch depend on the timing between master and slave clock
phases, as it will be shown later.
• Most common implementation of master-slave latch consists
of two serially connected identical latches transparent on
opposite levels of the input clock (complementary clock
phases).
• In this way, a master-slave latch behaves as an edge-triggered
storage element (see flip-flop below).
• If the master latch is transparent on the high level of the clock,
and the slave latch is transparent on the low level of the clock,
resulting MS latch is “falling-edge triggered”, otherwise it is
“rising-edge triggered”.
Figure 3. Master-slave latch: a) general configuration, b) connected as positive-edge
triggered storage element, c) timing diagrams for circuit in b )
 Flip-Flop
• Flip-flop is an edge-sensitive element with following
behavior: the output captures the value of the input either
after the low-to-high transition of the clock, or after the
high-to-low transition of the clock; otherwise, the flip-flop
is non-transparent, i.e. it holds the captured value at the
output.
• The transition of the clock that causes the change of the
output is referred to as capturing edge of the clock.
Depending on which clock edge is capturing, a flip-flop can
be rising-edge triggered, Figure 5, or falling-edge triggered.

Figure 4. Positiv edge-triggered flip-flop: a) function,

b) structure, c) timing diagrams
• Structurally, a flip-flop consists of two functional stages
(Figure 4b, ): Pulse generator, producing a pulse
synchronous to the active clock edge, depending on the
input value to be captured.

• As opposed to the operation of a pulsed latch, the pulse created by

the pulse generator of a flip-flop contains all information about
new data to be captured, and the second-stage latch is used only
to create a static output.
• Such pulse need not have determined short width, and it can be
chosen to facilitate the design of both pulse generator and the
latch.
• Set-reset latch that captures the pulse created by the pulse
generator. This latch changes its state to high if the “set” input is
active, and to low if the “reset” input is active; the latch keeps the
captured value otherwise
 Dual-Edge Triggered Storage Element
• Dual-edge triggered storage element is an edge-sensitive
element that captures the value of the input after both low-to-
high and high-to-low clock transitions. Otherwise, the storage
element is non-transparent, i.e. it holds the captured value at
the output.
A dual-edge triggered storage element can be classified as:
• Pulsed latch (Figure 5b), which consists of a clock pulse generator
and a transparent latch. The clock pulse generator creates a short
pulse after both clock edges, used as the clock input to the
transparent latch.
Figure 5. Dual-edge-triggered storage elements: a) function, b)
pulsed latch, c) flip-flop, d) latch-MUX
Flip-flop (Figure 5c), which consists of the same building blocks as
single-edge triggered flip-flops. The pulse generator is active on both
edges, or it combines the outputs of two pulse generators active at the
opposite clock edges.

Latch-MUX structure (LM, Figure 5d), which consists of two latches,

connected in parallel and transparent on opposite levels of the clock,
and a multiplexor that selects the output of the non-transparent latch at
any time. Latch-MUX is a dual-edge triggered counterpart of the master-
slave latch clocked with the complementary clock phases.
 Elements
A latch is characterized by the following
parameters:
• Set-up time - maximum allowed data arrival with
respect to the latching clock edge in order to
correctly capture it
• Hold time - minimum allowed data arrival after the
latching clock edge in order to correctly capture the
previous value
• Propagation time - delay between the releasing
clock edge and the latch output switching to the
new value
• Data-to-output delay - delay between the data
arrival and the output switching to the new value,
assuming that the latch is in the transparent mode
 Following are the basic timing parameters of a flip-
flop:
• Dual-edge triggered storage elements apply all parameters defined for the
single-edge triggered storage elements to the both clock edges. It is a custom
practice that the worse of the parameters for the two edges is used as the
only timing parameter. As the timing parameters for both clock edges
should always be taken into account.
• Set-up time - maximum allowed data arrival with respect to the
capturing clock edge in order to correctly capture it
• Hold time - minimum allowed data arrival after the capturing clock
edge in order to correctly capture the previous value.
• Propagation time (clock-to-output delay) - delay between the
capturing clock edge and the flip-flop output switching to the new
value