• Timing analysis refers too the analasisi of the design for timing issuse

• 1) STA 2) DTA
• Static ----> Analysis happens statically and does not depends on inputs
insted we use lookup tabels ,Timing models, Delay calculators to estimate
timings very accuratelly.
• Some ex of timing checks are
• 1) Setup check ---- > data arrived at ff with in the given clk period
• 2)Hold check -------> data held atleast minimum time their is no
unexpected pass through data {which means FF capture the data properly
or not}
• The purpose of the STA is to validate if the design can operate at rated speed
• One of the most important aspect of STA is that the entire design is analysed
once and the required timing checks are preformed for all the possible paths
and scenarios of the design.
• WHY STA ?
• It’s complete and exhaustive of all timing checks of a design
• Design implementation must be verified to be roobust which means it can
withstand the noise without affecting the rated performence of the design
• OCVs and PVTs can be modelled and handeled by STA
 STA DTA/Timing simulation

• no input stimulus {characterized • input stimulus given and also we to

Lookup table} taken cell delays from validate the output
.lib file from vendor net delays takes
from RC extraction
• validate functionality as well
• Dose not validate functionality
• Much slower than STA
• Faster for complex design
• Depends on the test vector
• Complete and Exhaustive process
Because it handel timing anlysis
without gvinen any input stimulus it
covers all the timing paths in entire
digtal design
• Can handel the effects of crosstalk and • its not accurate for crosstalk and
OCV accurately its very importent for OCV
advanced technology nodes • ideal for small designs like for std
• Ideal for large designs cell design
• can’t check wether all required FF in • can simulate reset
design are set to required values when
we hit the synchronous and • May can handel X also
asynchronus reset • Can check synchronizers
• Can’t handel X can understand only • Can identify flase paths
logic high and logic low
• cannot ensure the synchronizers in
asynchronous clock domain crossing
• Cannot identify false paths {signal
cannot flow from false paths }
DELAY AND SLEW IN CIRCUITS

• Delay is the time taken by signal to propagate from one point to another in a
circuit
• 2 Types of delays:
• 1) Cell delay or propagation delay of cell or gate delay is the time taken by the
signal to propagate through the gate
• 2) Wire delay or net delay or interconnect delay or extrinsic delay or flight time
is the delay due to parasitic on the net

• Slew or transition time is the time taken by the signal to change its state
INTRINSIC DELAY OF A CELL

• Intrinsic delay of a logic gate or cell is the cell delay for a near zero slew at the
input and no load connected to the output
• Intrinsic delay is minimum delay offered by the gate
• Factores affecting cell delay
• Supply Vlotage increses Delay Decreses
• Load at output pin increses Delay Increses
• Slew of signal at input pin increses Delay Increses
• Temperature Increses Delay Increses
PULSE WIDTH

• Pulse width is the duration of time for which the clock will stay
stable in a particular state
• In digital designn, clocks must have a minimum pulse width for
propose of the design
STA BEFORE PD
• In a CMOS digital design. STA can be performed at many different stages of the
implementation.
• STA is rarely performed at RTL level Because it’s very important to check the
functionality of design in RTL, and also there no timing information availabel at
RTL stage so in RTL stage we did’t do any timing analysis
• Once the design at RTL level has been synthhesized to the gate level, the STA
used to verify the timing of the design
• At the begining of logic design stage, ideal interconnect is assumed since there’s
no information about physical placement. (ZWLM)
• At this stage, main focus is on the logic that contribute to the worset paths.
• 1) After synthesis and before Logic optimization STA is done in order to detect
critical timinng paths
• logic optimization such as input reorder, input and output buffering, Power, speed or
performence and area optimization
• This logic optimization uderstand which path is critical for timing to do timing optimization
• 2) After Placement
• clock network is ideal
• At this stage we consider cell delays to because cell placed at this stage
• 3) After clock tree
• source and network latency
• clock skew and jitter and many other uncertinity information
• 4) After routing
• In this stage the DMF related fill happen
• this design send to extractor tool which extract RC extraction from metal
• coupling effect, crosstalk and noise to de checked
• this stage of STA is more accurate then other stages because in this stage we get real values of RC
• Summary
• STA depends on interconnect model
• STA is done with or without real clock tree
• STA is done by taking consideration of coupling effects such as crosstalk or not
Combinational logic hazards
• Boolean algebra assume that
variable value remain constant
during evaluation
• Change of variable values during
evaluation leads to incorrect
answer
• Asynchronous sequential circuits
are mostly uneffected
• Glitch is an unnwanted short pulse
• Glitch may not be a problem or may create havoc
• If we delay evaluation untill all propagation delays have transpired,
then hazards are not a problem
• If circuit speed is less than hazards, it’s not a problem
Hazard free circuit
• Switching equation F = yz + x`z`
• in cononical form F = xyz + x`yz +
x`yz` = x`y`z`
• Equation to be used F =x`z` + x`y
+ yz
Types of hazards
• Static hazards - These hazards are produced in steady state of input
• Static 1 hazard- Output is supposed to be 1 but momentarlly goes to 0
F=xy+y`z
• Static 1 hazard- Output is supposed to be 1 but momentarlly goes to 0
F=(x+y) . (y+`z)
• Dynamic Hazards - Output changes three or more times when it
should change only once during transition
• Happens due to difference in transition time of gates or speed of gates
What is a timing ARC ?
• A segment or component of a timing path that may contribute to the delay in
signal propagation along the path is represented by a timing Arc
• A timing Arc specifies the timing relationships between pins of logic elements
• Any timing information which influences the timing of a path is provided to STA
tool through a timing Arc.
Types of timing ARCS
• 2 types
• Delay Arc
• Cell Delay Arc
• Net Delay Arc
• Constraint Arc
• Each cell can have multiple delay and constraint Arcs
Cell Delay ARC
Delay Arc Examples
• Delay arc for an inverter:
Net delay Arc
• Net delay represents the delay due to the interconnect.
Constraint Arc
• Constraint arc are associate with
sequential cells only.
• it is defined for an input pin or
between input pins.
• Setup and hold arcs are examples of
constraint arcs defined between
input pins of a filp-flop.
• Minimum pulse width arc is an
example of constraints arc defined on
an input pin of a flip-flop.
What is a timing path
• In a digital design, data travel from input port to output port of the
design through series of sequentioal or combinational elements.
• A timing path in a design can be consider as collection of paths or
timing arcs
• In STA paths are timed based on the valid start points and valid end
points
• valid startpoints : input ports and output ports of synchronous device
• valid endpoints : output ports and data ports of synchronous elements
Types of timing paths
• From an input to output port (default ports)
• From input port to flip-flop (in to reg)
• From ff to ff (reg to reg)
• From ff to output port (reg to out)
Slak or margin
• The difference between Required arrival time and actual arrival time is
called slack or margin
• Slack = RAT - AAT
• Positive slack means the timing met. Negative slack means timing is
voilated by that amount.
Critical path
• A timing path that fails to meet the timing constraint by largest
margin in a design is called critical path.
• if all timing paths are meeting the constraints then the path that is
closest to falling is called critical path.
• Critical path determine the maximum frequency of operation of
design
What is virtual clock
• Virtual clocks are clocks that don’t physically exist in the specific block but
represent on external trigger that impacts the timing of the block.
• STA cannot check any timing on a path that is not constrained. thus, all
paths should be constrained to enable their analysis.
Why setup and hold checks?
• These synchronous checks are needed to ensure that dara is ready
and available for capture and held for at least a minimun time so
that there is no unexpected pass-through of data through flip-flop.
Defining setup and hold time
• Setup time of a flip-flop is the minimum time for which the data
needs to be stable before the arrival of active edge of the clock.
• Hold time is the minimum time for which the data needs to be stable
after the arrival of the active edge of the clock.