PD FLOW

B.DURAIMURUGAN
TRAINEE
TEAM HAWKEYE
VICANPRO TECHNOOGIES

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 PHYSICAL DESIGN

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 PHYSICAL DESIGN
• It is the process of transforming circuits
description into the physical layout
• It describes the position of cells and routes to
interconnect between them
• In floorplanning the cells can be placed in
layout
• After placement the routing can be done

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 INPUTS
• Gate level netlist
• Logical and physical information
• SDC
• UPF
• FP DEF and Scan DEF
• Technology File
• RC-Coefficent

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 FLOW DIAGRAM

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 PARTITIONING
• It can be done in RTL design phase
• Design engineers partitioning the entire design into
the sub-blocks and then proceed the module
• Module linked with main module it is called as top-
level module
• It is refered as logical partitioning

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 LEVEL OF PARTITIONING

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 SYNTHESIS

• Process of converting RTL to Gate Level Netlist

• RTL means Verilog code
• Gate Level Netlist means it’s include nets,sequential and
combinational cells

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 INPUTS,OUTPUTS AND GOALS
INPUTS:
Verilog file .v
Lib file
Lef file
SDC
Scan configuration
Floorplan DEF

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 OUTPUTS:
Netlist
SDC
UPF
Scan DEF
GOALS:
To get a gate level netlist
Inserting clock gates
Logical Optimization
Easy to Route

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 STEPS IN SYNTHESIS
• Analyze
• Elaborate
• Import Design
• Clock gating
• Compile
• Optimization
logical(Size , remove unused cells,)
Design(Power , Area ,Timing DRV’S,INC clock gating)

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 SANITY CHECKS
• Check LEC
• Check CLP
• Multi-Driven Inputs
• Check Timing
• Pin mismatch

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 FLOOR PLANNING

• It is a process of placing macros in core area.

• It determining the routing area between
them,wiretracks,I/O Placements.
• Two Stage
Macro Placement
Basic floor plan

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 INPUTS,OUTPUTS AND GOALS

INPUTS:
Gate Level Netlist
Lib file
SDC
Tech file

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 OUTPUTS:
Die/Block area
I/O placed
Macro placed
Power-Grid Design
Power pre-routing
Standard cell placement

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 GOALS

• Arrange the block on a chip

• Decide the location of the I/O pads
• Decide the location and number of the power pads
• Decide the types of power distribution
• Decide the location of clock distribution

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 CONTROL PARAMETER

• Aspect Ratio=Width/Height
• Core Utilization=Area of standard cells/Core Area +Channel Area
• Die Area
• Core size

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 QUALIFY THE FLOORPLAN

• Meets the floorplan constraints

• Minimize the total Chip area
• Routing Free Easy
• Reduce the Signal Delay

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 CHALLENGES

• Congestion
• IR –Drop
• Timing

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 FLOORPLAN GUIDELINES

• Flyline Analysis
• Placed macro near the I/O and boundary
• Provide Halo space to all macros
• Provide proper blockages

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 CHECKS

• Check CLP
• Row creation
• Macro Placed
• Power Glitches
• Check physical cells

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 PLACEMENT
• Placing Standard cells in the rows created at
floorplan stages
• Automation Process
• Consraints
Total wirelength
Timing
Congestion
Power

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 INPUTS,OUTPUTS AND GOALS
• INPUTS:
Netlist
Logical and Physical Libraries
Design Constraints
• OUTPUTS:
Physical Layout Information
Cell placement location

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 GOALS

• Timing, Area, Power Optimization

• Routable Design
• Minimal Cell and Pin Density
• Minimal Timing DRC’S

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 CHALLENGES

• High Fan-Out
• Scan Chain Reordering
• Special Cell adding

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 OPTIMIZATION TECHNIQUE

• Cloning
• Gate Sizing
• Buffering
• Redesigning Fanout trees
• Swapping pins

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 CHECKS
• Check Legalization
• Check PG Connection
• Check congestion, place and pin’s density
• Timing QR
• Timing DRV’S
• Don’t use cells
• Don’t touch
• Check setup timing

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 CLOCK TREE SYNTHESIS

• It is the important stages in PnR

• It is the process of inserting buffers and inverters along the clock
paths
• Balance clock delay
• Before CTS all clock pins are driven by a single clock

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 INPUTS AND OUPUTS OF CTS

INPUTS:
Detailed Placement Database
CTS Constraints
SDC
OUTPUTS:
DEF
SPEF

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 GOALS OF CTS
1. Meet the clock tree constraints
Max Transistions
Max Capacitance
Max Fanout
2. Meet the clock tree targets
Minimum Skew
Minimum Insertion Delay

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 EFFECTS OF CTS
Signal Integrity
It is the ability of an electrical signal to carry information
reliably
It resist the effects of high frequency electromagnetic
interference from near by signals
Some of the effects are
1.Crosstalk
2.Electromigration
3.Antenna Effect

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 Crosstalk:
Undsirable electrical interaction between two or more nodes
due to capacitive coupling
Crosstalk effects became increasingly important compared to
cell and net delays
Effects:
Signal should be constant for sometime
Transistion in adjacent signal causes anoises/glitches on constant
signal

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 HOW TO FIX CROSSTALK ISSUE

1. Double Spacing
2. Multiple Vias
3. Shielding
4. Buffer Insertion

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 ELECROMIGRATION
1. Opens and shorts due to metal ion displacement caused by a flow of
electron in metal
2. Lead to functional failures of IC
3. Reason: Increase in current densities in net

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 HOW TO PREVENT
ELECTROMIGRATION ISSUES

1. Inserting buffers and inverters with non default rule

2. Increasing width of the wire
3. Routing the metal in higher metal layers
4. Up-Sizing the cells

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 ANTENNA EFFECT
During the fabrication of MOS integrated circuits ,especially at
the plasma etching,there will be a chance of collecting more
charges at the gate and causes damage to gate oxide layer and it is
very thin. This is called as Antenna Effect

ANTENNA VIOLATION= Gate Area/Gate Oxide

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 SOLUTION FOR ANTENNA
VIOLATIONS
Metal Jumper:
Breaks signal wires and route to upper metal layers
Delay Insertion:
1.Connect reverse biased diodes near the gate input
where violation occurs on a net provide a discharge path to substrate to
save the gate
2.Adding diodes increases the area and also the
capacitance which lead to insertion delay

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 CTS OPTIMIZATION TECHNIQUES

1. Buffer Relocation
2. Gate Relocation
3. Buffer Sizing
4. Gate sizing
5. Delay Insertion
6. Dummy load insertion
7. Minimize Skew

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 SETUP AND HOLD TIME
SETUP:
It is the interval before the clock where the data must be
held stable
FORMULA:
Datapath=max(wire delay to clock input FF1)+max(clock to
Q delay of FF1)+max(cell delay of inverter)+max(2wire delay
of Q of FF1 to inverter and inverter to D of FF2)
Clockpath=clock period+min(delay fom clock to buffer
input)+min(cell delay of buffer)+min(delay from buffer outputto
FF2 clock pin)-setup time of FF2
SetupTime=Tclk-Td
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 HOW TO FIX SETUP AND HOLD
VIOLATION
SETUP:
1.Up-Sizing the cell
2.Pull the launch clock
3.Push the capture clock
4.Reduce the Buffer
5.Replace the Buffer with two inverters
6.Increase the Repeaters
7.VT Swapping, Adding Delay
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 HOLD:
It is the interval after the clock where the data must be held stable
FORMULA:
Datapath=min(wire delay to clock input FF1)+min(clock to Q
delay FF1)+min(cell delay of inverter)+min(2wire delay of Q of FF1 to
inverter and inverter to D of FF2)
Clockpath=clock period+max(delay from clock to buffer input)
+max(cell delay of buffer)+max(delay from buffer output to FF2 clock
pin)+hold time of FF2
Holdtime=Td-Tclk

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 HOLD:
1.Downsizing the cells
2.Pulling the capture clock
3.Pushing the launch clock
4.Adding buffers/inverters to datapaths
5.Decrease the size of certain cells in data paths

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 CTS EXCEPTIONS
• Stop Pin:
All clock pins of FF are called as Stop pins
• Exclude Pin:
All clock pins of D pin or FF pin or combo logic inputs are
called as Exclude Pin
• Float Pin:
Internal clock latency
• Explicit Sync Pin:
Input of Combo logic

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 SANITY CHECKS

• Check Legality
• Timings DRV’S
• High Fan Out
• Congestion
• Don’t Use Cells
• Don”t Use Attributes
• Pre-existing cells in clock paths are balanced cells
• PG Connections

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 ROUTING

• Interconnection of standard cells, macros and

I/O
• Electrical connections using metals and vias
defined by logical connections

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 INPUTS,OUTPUTS AND GOALS
INPUTS:
CTS Constraints
Signal nets
OUTPUTS:
GDS
Verilog
Power Information Verilog
LEF
DEF
UPF
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 TASK
• Global Routing
• Detailed Routing
• Track Assignment
• Search and Repair

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 GLOBAL ROUTING
• Split the area to G cells to tie cells
• Tie to Tie connection to optimize
Sequential
Net Re-ordering
Concurrent
Bsed on Patterned Routing
Different shape to route

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 DETAILED ROUTING

• It ues the routing plan

• To complete all the required interconnect without leaving open and
shorts
• Starts with routing divider to convert the block into specific cells
called switch box

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 SEARCH AND REPAIR,TRACK
ASSIGNMENT

• It performed during detailed routing after the first iteration

• When there is an open or shorts are located and they should be rerouting
in a affected areas
Track Assignment:
Tracks are assigned for each global routes
Assign in both horizontal and vertical
Re-routing at overlapped areas

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 GOALS
• Minimize the wirelength
• Minimize the critical path
• Minimize the number of layer
• Meets Timing DRC
• Minimize the congestion hotspot

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 CHECKS
• Check LEC
• Check CLP
• Check PG connection
• Check whether the filler cells are inserted or not
• Check whether the decap will be inserted or not
• Check all cells are routed

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 SIGN-OFF

• Layout will be ready after the routing

• Some checks we have to perform
• They are as follows

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 LVS CHECK
• Given layout satisfies the design rule provided by fabrication unit
• Check functionality matched or not
• Locate the mismatch
• Errors
Shorts
Open
Parameter Mismatch

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 DRC CHECKS
• Physical check of metal width, Pitch, Spacing of different metal layer
• Physical connection doesn’t considered DRC it will lead to failure of
functionality
• Common DRC Rules:
Interior
Exterior
Enclosure
Extension

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 LEC CHECKS

• Checks Functionality
• Inputs are Golden=Pre-layout Design
• Output are Revised=Post-layout Design
• Check Timing

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 XOR CHECK

• Difference of Two GDS

• Checks whether it has open or shorts
• Checks Logical connection

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 ERC CHECK

• Check Secondary PG connection

• Check electrical connectivity
• Checks whether it has open or shorts

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 PERC CHECK

• Inputs=Routed.V
• Electrostatic Discharge
• Muliple Power Domain
• Check electrical connectivity

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 CLP CHECK

• Check low power connections

• Check Multiple power domain

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 THANK YOU
B.DURAIMURUGAN
TRAINEE
TEAM HAWKEYE
VICANPRO TECHNOLOGIES

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