*info: Placed = 18624 (Fixed = 3325)

*info: Unplaced = 0
Placement Density:68.25%(141842/207822)
Placement Density (including fixed std cells):68.89%(146108/212088)
PowerDomain Density <PD1>:0.00%(0/16279)

There are 6 clock nets ( 6 with NDR )

Total clock nets wire length: 5.713000e+01um

For timing_corner Max_delay:setup, late:

Slew time target (leaf): 0.200ns
Slew time target (trunk): 0.200ns
Slew time target (top): 0.200ns (Note: no nets are considered top nets in
this clock tree)
Buffer unit delay for power domain PD1: 0.145ns
Buffer max distance for power domain PD1: 1030.423um
Buffer unit delay for power domain TOP: 0.145ns
Buffer max distance for power domain TOP: 1030.423um

Timing corner Max_delay:setup.late:

Skew target: 0.145ns