Routing

Agenda
• Objectives
• Inputs & Outputs
• Core Steps Involved in Routing
• ICC Routing Flow
Objectives
• To achieve 100% routability

• Minimize total wire length, the number of vias without increasing the

chip area

• Meet the timing budget for each net

• Minimizing Physical and Logical DRCs

Inputs
• Placement db

• Technology File

• Routing Constraints /Options /Libraries

Outputs
• Routed design

• Routing Congestion Map/Reports

 Basic Routing Flow
FROM CTS CLOCK ROUTING GLOBAL ROUTING

SIGNAL ROUTING TRACK ASSIGNMENT

CLOCK ROUTING
CLOCK ROUTING DETAIL ROUTING
POST ROUTE OPT SEARCH & REPAIR

EXTRACTION &
BACKANNOTATION

STA
 GLOBAL ROUTING

• Divides the design area into regions/tiles/gcells

• Assigns nets to these regions and also respective metal layers

• Determines which gcell to gcell path a net(s) has to take

• Does not assign any nets to the tracks

• Initial Routing phase & Re-routing phase

• At the end saves the g-links & g-vias

• Global Route Congestion Report
• Global Route Congestion Map
• Global Route Congestion Map
 TRACK ASSIGNMENT

• Assigns a track to each Global route

• Attempts to make long and straight traces

• Reduces the number of vias

• Does not honour DRC rules

• At the end no more global routes exist

• All nets are routed/plenty of violations/nets to pins

• Track Assignment Report
 DETAIL ROUTING

• Completes and Validates the routing according to Design Rules

• Uses rectangular Switch Boxes (S-box)

• Traverses multiple S-boxes progressively and fixes DRCs/Antennas

• Fixing limited to current S-box

• Detail Routing Report
 Before Routing..!
• Library Requirements Tech File & Libs
• Design Reqs.
• PG Nets Routed
• Placement
• CTS & Optimization
• Timing—Acceptable—0 slack
• Max. tran & cap – No violations!

• Check_zrt_routability
• Blocked std cell ports
• Macro ports
• Out of boundary pins
• Min. grid violations
 IC Compiler Routing Flow
• Zroute
• Global Router
• Track Assigner
• Detail Router
• ECO Router Few Features of Zroute router…
• Specially designed for nodes <45nm
• Concurrent integration of DFM steps like redundant
via insertion during detail routing
• Concurrent optimization of design rules, antenna
rules, wire optimization, and via optimization during
detail routing
• All engines are timing and crosstalk driven
• Intelligent design rule handling -merging of redundant
design rule violations
ICC Routing Chronology….
• Step 1: Setting Routing Constraints and Options

• Step2: Routing Clock Nets & Post clock route opt

• Step3: Routing Critical Nets

• Step4: Routing Signal Nets

• Step5: Performing Post-Route Optimizations

• Step6: Extract RC and STA

Step1: Setting Routing Constraints and Options
• Setting Routing Constraints
• Route Guides
• Non-Default Routing Rules (NDRs)
• Create_route_guide
-no_signal_layers
-preferred_direction_only_layers
-horizontal_track_utilization%
-vertical_track_utilization%

• 1. Define_routing_rule
• 2. set_clock_tree_options
• 3. set_net_routing_rule
Step1: Setting Routing Constraints and Options (Contd..)
• Setting Routing Options

• Set_route_zrt_common_options
• Set_si_options –route_xtalk_prevention true
• Set_route_zrt_common_options –enforce_voltage_areas
Step2: Routing Clock Nets

• Route_zrt_group –all_clock_nets

• Performs GR, TA , DR for all clock nets

• Also redundant via insertions and clock net shielding

• Post Route Clock tree optimization

• optimize_clock_tree -routed_clock_stage detail -buffer_sizing

-gate_sizing
Step3: Routing Critical Nets

• Routing Corridors

• create_routing_corridor
Step4: Routing Signal Nets

• Can be performed in 2 ways :-

• Standalone Commands
• Route_zrt_global
• Route_zrt_track
• Route_zrt_detail

• Core Command
• Route_opt
Step5: Post Route Optimization
• Route_opt

• Fixes setup, hold, DRVs altogether

• Concurrent data & clock path optimization
• Leakage power, Area recovery
• High resistance optimization

• Focal_opt

• Aggressively tries to fix one entity at a time

Step6: RC Extraction

• Extract_rc

• StarRC/ Quantus
Thank You!