1.

Error browser

icc2_shell> check_pg_drc

Command check_pg_drc started at Mon Oct 24 22:16:31 2022

Command check_pg_drc finished at Mon Oct 24 22:16:32 2022

CPU usage for check_pg_drc: 1.16 seconds ( 0.00 hours)

Elapsed time for check_pg_drc: 1.16 seconds ( 0.00 hours)

Total number of errors found: 5

1 insufficient spacing on M2

4 insufficient spacings on M5

------------

Description of the errors can be seen in gui error set "DRC_report_by_check_pg_drc"

------------
icc2_shell>

2.report_qor

icc2_shell> report_qor

Information: Timer using 1 threads

Warning: Technology layer 'M4' setting 'pitch' is not valid (NEX-001)

Warning: Technology layer 'MRDL' setting 'pitch' is not valid (NEX-001)

****************************************

Report : qor

Design : ChipTop

Version: S-2021.06-SP4

Date : Mon Oct 24 22:03:37 2022

****************************************

Warning: Corner fast: 1 process number, 0 process label, 0 voltage, and 0 temperature mismatches.
(PVT-030)

Warning: 4 cells affected for early, 4 for late. (PVT-031)

Warning: 0 port driving_cells affected for early, 0 for late. (PVT-034)

Warning: Corner slow: 1 process number, 0 process label, 0 voltage, and 0 temperature mismatches.
(PVT-030)

Warning: 4 cells affected for early, 4 for late. (PVT-031)

Warning: 0 port driving_cells affected for early, 0 for late. (PVT-034)

Information: The stitching and editing of coupling caps is turned OFF for design
'chiptop_lib:route_design_4short.design'. (TIM-125)

Information: Design route_design_4short has 7415 nets, 0 global routed, 7414 detail routed. (NEX-024)

Warning: Technology layer 'M4' setting 'pitch' is not valid (NEX-001)

Warning: Technology layer 'MRDL' setting 'pitch' is not valid (NEX-001)

Information: The RC mode used is DR for design 'ChipTop'. (NEX-022)

---extraction options---
Corner: slow

late_cap_scale :1

late_res_scale :1

early_cap_scale :1

early_res_scale :1

Corner: fast

late_cap_scale :1

late_res_scale :1

early_cap_scale :1

early_res_scale :1

Global options:

reference_direction : use_from_tluplus

real_metalfill_extraction : none

virtual_shield_extraction : true

---app options---

host.max_cores :1

extract.connect_open : true

extract.incremental_extraction : true

extract.enable_coupling_cap : false

Extracting design: route_design_4short

Information: coupling capacitance is lumped to ground. (NEX-030)

Information: 7413 nets are successfully extracted. (NEX-028)

Warning: Advanced receiver model has not been enabled for detailed routed design. (TIM-204)

Information: Update timing completed net estimation for all the timing graph nets (TIM-111)
Information: Net estimation statistics: timing graph nets = 7413, routed nets = 7413, across physical
hierarchy nets = 0, parasitics cached nets = 7413, delay annotated nets = 0, parasitics annotated nets =
0, multi-voltage nets = 0. (TIM-112)

************************************************************

Timer Settings:

Delay Calculation Style: auto

Signal Integrity Analysis: disabled

Timing Window Analysis: disabled

Advanced Waveform Propagation: disabled

Variation Type: fixed_derate

Clock Reconvergence Pessimism Removal: disabled

Advanced Receiver Model: disabled

ML Acceleration: off

************************************************************

Scenario 'func_fast'

Timing Path Group 'in2reg'

----------------------------------------

Levels of Logic: 7

Critical Path Length: 1.97

Critical Path Slack: 1.46

Critical Path Clk Period: 3.30

Total Negative Slack: 0.00

No. of Violating Paths: 0

Worst Hold Violation: 0.00

Total Hold Violation: 0.00

No. of Hold Violations: 0

----------------------------------------

Scenario 'func_fast'

Timing Path Group 'reg2out'

----------------------------------------

Levels of Logic: 7

Critical Path Length: 0.58

Critical Path Slack: 1.13

Critical Path Clk Period: 3.30

Total Negative Slack: 0.00

No. of Violating Paths: 0

Worst Hold Violation: 0.00

Total Hold Violation: 0.00

No. of Hold Violations: 0

----------------------------------------

Scenario 'func_fast'

Timing Path Group 'reg2reg'

----------------------------------------

Levels of Logic: 10

Critical Path Length: 0.85

Critical Path Slack: 2.18

Critical Path Clk Period: 3.30

Total Negative Slack: 0.00

No. of Violating Paths: 0

Worst Hold Violation: -0.03

Total Hold Violation: -0.24

No. of Hold Violations: 54

----------------------------------------

Scenario 'func_slow'

Timing Path Group 'reg2reg'

----------------------------------------

Levels of Logic: 10

Critical Path Length: 0.92

Critical Path Slack: 2.30

Critical Path Clk Period: 3.30

Total Negative Slack: 0.00

No. of Violating Paths: 0

Worst Hold Violation: 0.00

Total Hold Violation: 0.00

No. of Hold Violations: 0

----------------------------------------

Cell Count

----------------------------------------

Hierarchical Cell Count: 2

Hierarchical Port Count: 362

Leaf Cell Count: 7600

Buf/Inv Cell Count: 3117

Buf Cell Count: 2294

Inv Cell Count: 823

CT Buf/Inv Cell Count: 0

Combinational Cell Count: 6886

Single-bit Isolation Cell Count: 0

Multi-bit Isolation Cell Count: 0

Isolation Cell Banking Ratio: 0.00%

Single-bit Level Shifter Cell Count: 0

Multi-bit Level Shifter Cell Count: 0

Level Shifter Cell Banking Ratio: 0.00%

Single-bit ELS Cell Count: 0

Multi-bit ELS Cell Count: 0

ELS Cell Banking Ratio: 0.00%

Sequential Cell Count: 714

Integrated Clock-Gating Cell Count: 0

Sequential Macro Cell Count: 4

Single-bit Sequential Cell Count: 710

Multi-bit Sequential Cell Count: 0

Sequential Cell Banking Ratio: 0.00%

BitsPerflop: 1.00

Macro Count: 4

----------------------------------------
Area

----------------------------------------

Combinational Area: 2376.20

Noncombinational Area: 778.86

Buf/Inv Area: 930.89

Total Buffer Area: 768.96

Total Inverter Area: 161.93

Macro/Black Box Area: 26672.12

Net Area: 0

Net XLength: 81876.79

Net YLength: 60367.11

----------------------------------------

Cell Area (netlist): 29827.18

Cell Area (netlist and physical only): 30434.22

Net Length: 142243.90

Design Rules

----------------------------------------

Total Number of Nets: 7508

Nets with Violations: 98

Max Trans Violations: 0

Max Cap Violations: 98

----------------------------------------

icc2_shell> report_utilization

****************************************

Report : report_utilization

Design : ChipTop

Version: S-2021.06-SP4

Date : Mon Oct 24 22:08:00 2022

****************************************

Utilization Ratio: 0.2048

Utilization options:

- Area calculation based on: site_row of block route_design_4short

- Categories of objects excluded: hard_macros macro_keepouts soft_macros io_cells

hard_blockages

Total Area: 62393.0112

Total Capacity Area: 15298.2864

Total Area of cells: 3133.0416

Area of excluded objects:

- hard_macros : 26888.3275

- macro_keepouts : 20362.0620

- soft_macros : 0.0000

- io_cells : 0.0000

- hard_blockages : 0.0000

Utilization of site-rows with:

- Site 'unit': 0.2048

0.2048

icc2_shell> report_clock_qor

Info: Initializing timer in CLOCK_SYN_REPORT_MODE

Information: The value of option cts.compile.enable_cell_relocation has been overridden to "leaf_only"

to support latency-driven placement. (CTS-973)

****************************************

Report : clock qor

-type summary

Design : ChipTop

Version: S-2021.06-SP4

Date : Mon Oct 24 22:08:59 2022

****************************************

Attributes

===========

M Master Clock

G Generated Clock

& Internal Generated Clock

U User Defined Skew Group

D Default Skew Group

* Generated Clock Balanced Separately

===========================================

==== Summary Reporting for Corner fast ====

===========================================
======================================================= Summary Table for Corner fast
========================================================

Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap
DRC Wire

Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Length

Count Area Area

-------------------------------------------------------------------------------------------------------------------------------------------
---

### Mode: func, Scenario: func_fast

clock M,D 586 9 90 30.33 30.33 0.43 0.11 0 0 3040.62

-------------------------------------------------------------------------------------------------------------------------------------------
---

All Clocks 586 9 90 30.33 30.33 0.43 0.11 0 0 3040.62

Warning: Please use -largest / -smallest / -all switches with -show_verbose_paths / -show_paths to
report the clock paths. (CTS-956)

===========================================

==== Summary Reporting for Corner slow ====

===========================================

======================================================= Summary Table for Corner slow

========================================================

Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap
DRC Wire

Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Length
 Count Area Area

-------------------------------------------------------------------------------------------------------------------------------------------
---

### Mode: func, Scenario: func_slow

clock M,D 586 9 90 30.33 30.33 0.28 0.12 0 0 3040.62

-------------------------------------------------------------------------------------------------------------------------------------------
---

All Clocks 586 9 90 30.33 30.33 0.28 0.12 0 0 3040.62

Warning: Please use -largest / -smallest / -all switches with -show_verbose_paths / -show_paths to
report the clock paths. (CTS-956)

icc2_shell> report_clock_qor -show_paths -smallest 2

Info: Initializing timer in CLOCK_SYN_REPORT_MODE

Information: The value of option cts.compile.enable_cell_relocation has been overridden to "leaf_only"

to support latency-driven placement. (CTS-973)

****************************************

Report : clock qor

-type summary

-show_paths

Design : ChipTop

Version: S-2021.06-SP4

Date : Mon Oct 24 22:10:01 2022

****************************************

Attributes
===========

M Master Clock

G Generated Clock

& Internal Generated Clock

U User Defined Skew Group

D Default Skew Group

* Generated Clock Balanced Separately

===========================================

==== Summary Reporting for Corner fast ====

===========================================

======================================================= Summary Table for Corner fast

========================================================

Clock / Attrs Sinks Levels Clock Clock Clock Max Global Trans DRC Cap
DRC Wire

Skew Group Repeater Repeater Stdcell Latency Skew Count Count

Length

Count Area Area

-------------------------------------------------------------------------------------------------------------------------------------------
---

### Mode: func, Scenario: func_fast

clock M,D 586 9 90 30.33 30.33 0.43 0.11 0 0 3040.62

-------------------------------------------------------------------------------------------------------------------------------------------
---

All Clocks 586 9 90 30.33 30.33 0.43 0.11 0 0 3040.62

 & = Offset derived from max_clock_tree_path / min_clock_tree_path

r = latency reported is for a rising edge triggered event at the sink

f = latency reported is for a falling edge triggered event at the sink

Showing 2 smallest datapoints per clock / skew group (L=largest, S=smallest)

=========================================== Details Table for Corner fast

============================================

Clock / Sink Launch Capture Late Early

Skew Group Name Latency Latency Offset Offset

----------------------------------------------------------------------------------------------------------------------

### Mode: func, Scenario: func_fast

clock

S GPRs/GPR8_reg_reg_7_/CK 0.33 r 0.33 r -- --

S GPRs/GPR3_reg_reg_11_/CK 0.33 r 0.33 r -- --

======================================

==== Path Reports for Corner fast ====

======================================

Reporting paths for 2 smallest datapoints per clock / skew group

---------------------------------------------

Smallest Path #1

Mode : func
Corner : fast

Scenario : func_fast

Skew Group : default_clock

Clock Fanout : clock

Clock at Sink : clock

Sink : GPRs/GPR8_reg_reg_7_/CK

Latency : 0.33

---------------------------------------------

Point Fanout Cap Trans Incr Path

----------------------------------------------------------------------------------------------

source latency 0.00 0.00

clock (in) 1 6.50 0.33 0.00 0.00 r

cts_trgdly_21249/A (SAEDHVT14_DEL_R2V3_2) 0.33 0.00 0.00 r

cts_trgdly_21249/X (SAEDHVT14_DEL_R2V3_2) 1 4.97 0.03 0.22 0.22 r

cts_trgdly_21253/A (SAEDHVT14_DEL_R2V2_2) 0.03 0.00 0.22 r

cts_trgdly_21253/X (SAEDHVT14_DEL_R2V2_2) 1 9.66 0.05 0.07 0.29 r

cto_buf_drc_17517/A (SAEDLVT14_BUF_12) 0.05 0.00 0.29 r

cto_buf_drc_17517/X (SAEDLVT14_BUF_12) 11 13.77 0.01 0.02 0.31 r

ZCTSBUF_20957_17449/A (SAEDLVT14_BUF_S_4) 0.01 0.00 0.31 r

ZCTSBUF_20957_17449/X (SAEDLVT14_BUF_S_4) 11 9.04 0.01 0.01 0.33 r

GPRs/ZCTSNET_544 (GeneralPurposeRegisters) 11 9.04 0.01 0.00 0.33 r

GPRs/GPR8_reg_reg_7_/CK (SAEDHVT14_FSDPQB_V2LP_2) 0.01 0.00 0.33 r

----------------------------------------------------------------------------------------------

total clock latency 0.33

check_lvs -checks {open short} -max_errors 100000

===============================================================

Maximum number of violations is set to 100000

Abort checking when more than 100000 violations are found

All violations might not be found.

===============================================================

Total number of input nets is 7508.

Total number of short violations is 80973.

Total number of open nets is 1.

Open nets are VDD

Elapsed = 0:00:06, CPU = 0:00:06

icc2_shell> check_pg_connectivity

Information: The command 'check_pg_connectivity' cleared the undo history. (UNDO-016)

Loading cell instances...

Number of Standard Cells: 9994

Number of Macro Cells: 4

Number of IO Pad Cells: 0

Number of Blocks: 0

Loading P/G wires and vias...

Number of VDD Wires: 161

Number of VDD Vias: 1742

Number of VDD Terminals: 83

**************Verify net VDD connectivity*****************

Number of floating wires: 0

 Number of floating vias: 0

Number of floating std cells: 0

Number of floating hard macros: 0

Number of floating I/O pads: 0

Number of floating terminals: 0

Number of floating hierarchical blocks: 0

************************************************************

Overall runtime: 0 seconds.

icc2_shell>

icc2_shell> report_global_timing

****************************************

Report : global timing

-format { narrow }

Design : ChipTop

Version: S-2021.06-SP4

Date : Mon Oct 24 22:20:02 2022

****************************************

No setup violations found.

Hold violations

--------------------------------------------------------------

Total reg->reg in->reg reg->out in->out

--------------------------------------------------------------
WNS -0.03 -0.03 0.00 0.00 0.00

TNS -0.24 -0.24 0.00 0.00 0.00

NUM 54 54 0 0 0

--------------------------------------------------------------