Time Borrowing in Tempus/Innovus for Latch

Based Designs
Tool Version 18.1 or later
February 2019
Topics Covered

1. Basic Concept of Time Borrowing

2. Different Time Borrowing Modes in Tempus/Innovus
3. Max Time Borrow Mode
4. “Time Borrow” & “Time Given” calculation
5. Limiting Time Borrowing
6. What is “Borrow Edge Adjust”
7. Latch Through Mode
8. A few Practical Application

2 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

What is Time Borrowing / Cycle Stealing

For Flops, data arrival later than capture clock edge causes SETUP violation
Whereas Latch remains transparent for entire duration of active clock edge, relaxing
arrive-before-edge criterion.

Consequences :
• Data can arrive later than capture clock arrival and borrow from the next clock cycle !
This is called Time Borrowing or Cycle Stealing and the current stage Slack
improves

• Time available for the next stage reduces, but no adverse effect if next-stage delay
(from latch to next endpoint) is short

Time Borrowing allows paths to the latch and starting from it evade timing violations

3 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Time Borrowing Modes in Tempus/Innovus
Max Time Borrow (default):
• Analyzes single-segment paths between latches
• Enabled by the global setting

set_global timing_use_latch_time_borrow true ( do not use with set_analysis_mode )

or
set_analysis_mode –timingBorrowing true

Latch Through Mode:

• Analyzes paths through latches without breaking into segment
• Provides overall visibility of timing paths through latches and less pessimistic
• Improves timing and power optimization

set_global timing_enable_latch_thru_mode true

set_global timing_cppr_propagate_thru_latches true

4 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Time Borrowing Analysis

D Q D Q
D Q C1 C2
L2 L3
L1 8.92 0.77
G G
G

CLK1
CLK2 Assumptions:
Borrow Time= 8.92-5 =3.92 Setup = 0.0
D->Q delay = 0

C1+C2=9.69 < 10.0

C1 (late data arrival) (Required Time at L3)

L2 opening edge C2 L2 closing edge

Time to 0.77
start
point=3.92 8.92 9.69 20
5 0 5
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
 Slack Calculation and Max Borrow Time (Ideal)
1 2 3

Arrival after Closing Edge :

Arrival before Opening Arrival when Latch Slack < 0
Edge: Transparent : Time Borrow = Max borrow Time
Slack >=0 Slack=0
No Time Borrow / Negative Time Borrow > 0
Time Borrow

L2 opening edge Borrow time

L2 closing edge

Maximum borrow Time

(ideal)
20
6 0 5
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
Maximum Borrow Time Adjustment
Maximum Borrow Time
= Earliest Latch Open Edge – Latest Latch closing edge

Factors Affecting Edge Positions of Capture Clock

1. Library SETUP constraint of the endpoint latch
2. Open vs Close edge Clock Network Latency
3. Open vs Close edge Clock Uncertainty and Jitters
4. Open vs Close edge CPPR

NOTE:
CPPR reduces Pessimism while Uncertainty(skew) & Jitter increases it

7 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 Max Borrow Time Adjustment (Library Setup Time)
D Q D Q D Q
C1 C2
L1 L2 0.77 L3
8.00
G G G

CLK1
CLK2 L2 library Setup = 0.4
Borrow Time= 8.00-5 =3.00 D->Q delay =0
C1 (late data arrival)

L2 setup time=0.4

L2 opening edge
L2 closing edge

Maximum Borrow Time

=5-0.4=4.60 20
0 5
8 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
 Max Borrow Time Adjustment (Setup + Latency)

D Q D Q D Q
C1 C2
L1 L2 0.77 L3
8.00
G G G

CLK1
CLK2

Borrow Time= 8.00-5 =3.00 L2 library Setup = 0.4

C1 D->Q delay = 0
2.3 1.3
Rise latency = 2.3
L2 setup time=0.4 Fall latency = 1.3

2.3 L2 opening edge 1.3

1.3
L2 closing edge

Maximum Borrow Time

=5-0.4 – (2.3-1.3)=3.60
20
9 0 5
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
 Max Borrow Time Adjustment (Setup + Latency + Uncertainty)
D Q D Q D Q
C1 C2
L1 L2 0.77 L3
8.00
G G G

CLK1
CLK2
L2 library Setup = 0.4
Borrow Time= 8.00-5 =3.00 D->Q delay = 0
C1 Rise latency = 2.3
2.3 1.3 Fall latency = 1.3
L2 opening L2 setup time=0.4 Rise Uncertainty = 2.1
Fall Uncertainty = 1.8
edge 1.8
2.1 L2 closing
1.3 2.3 1.3
edge

Maximum Borrow Time =5-0.4 – (2.3-1.3)+(2.1-1.8)=3.90

20
10 0 5
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
 Max Borrow Time (Setup + Latency + Uncertainty + CPPR)
D Q D Q D Q
C1 C2
L1 L2 0.77 L3
8.00
G G G
CPPR branch
CLK point

Borrow Time= 8.00-5 =3.00 L2 library Setup = 0.4

Rise latency = 2.3
C1 Fall latency = 1.3
2.3 1.3 Rise Uncertainty = 2.1
L2 opening L2 setup time=0.4 Fall Uncertainty = 1.8
CPPR rise = 0.3
edge CPPR fall = 0.2
2.1 L2 closing
1.3 0.3 1.8 0.2
edge

Maximum Borrow Time =5-0.4–(2.3-1.3)+(2.1-1.8) – (0.3-0.2)=3.80

20
11 0 5
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. 10 15
Max Borrow Time

Max Borrow Time = W - S - ∆L - ∆CPPR + ∆U + ∆J

Where,
W : Nominal Pulse Width of Capture clock ( Latch Close Edge – Latch Open Edge)
S : Library SETUP constraint of the endpoint latch
∆L : Clock latency of Latch Open Edge – Clock latency of Latch Close Edge
∆U : Clock Uncertainty of Latch Open Edge – Clock Uncertainty of Latch Close Edge
∆ CPPR : CPPR for Latch Open Edge – CPPR for Latch Close Edge
(rising edge vs falling edge CPPR)
∆J : Clock jitter of Latch Open Edge – Clock Jitter of Latch Close Edge

Time Borrowed = (Latest data arrival time – Earliest open clock edge arrival time)

12 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Debugging Time Borrow
Max Borrow Time = W - S - ∆L - ∆CPPR + ∆U + ∆J
Use –debug time_borrow option with report_timing to get detailed calculation

Time Borrow Calculations

________________________
∆L = 0.0
Latch Early Close Edge 1.071
∆CPPR = (0.087-0.099) = -0.012
- Library Setup 0.043
∆U = (0.130-0.130) = 0
+ Close Edge Cppr 0.099
S = 0.043
- Close Edge Uncertainty 0.130 W = (1.071 – 0.627) = 0.444
- Latch Early Open Edge 0.627 ∆J =0
- Open Edge Cppr 0.087
+ Open Edge Uncertainty 0.130 Max Borrow Time
= Max Allowed Borrow Time 0.413 = W –S -∆L - ∆CPPR + ∆U + ∆J
- Time Borrowed 0.413 = 0.444-0.043 -0.0 – (-0.012)=0.413
= Available Time Borrow 0.000

13 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 Negative Time Borrow
Data Arrival Time at Endpoint Latch very close to open clock edge
(Data arrival late)

C1

Data arrival time + D->Q delay > Earliest clock open edge arrival time + Clk->Q delay
Negative Time Borrow
When (Data arrival time =~ Earliest clock open edge arrival time)
D->Q delay > Clk->Q delay dominates the equation

Max Negative Time Borrow: Data departure time at start point determined by D->Q delay and
D->Q delay – Clk->Q delay arrival time (instead of Clk->Q delay)

1.1
D Q

14 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

G
Is Time Borrowed Always Equal to Time Given?

Data arrival time at endpoint

= Data launch time for next stage

SETUP check : Late data arrival against early open edge

For path ending on latch, early clock edge considered
Actual time borrow For path starting from latch, late clock edge considered
CPPR reflects the difference between early and late clock edges

Time Given To Start Point

Adjustment for
clock uncertainty Late Latch Open Edge for path starting from latch (start time for next stage)
and CPPR
15 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Time Given Calculation
In Transparent mode, data arrival time at endpoint is also the data launch time for next
stage.
Time borrowed calculated using shifted edges if CPPR / Uncertainty exists at open clock
edge

Adjustment due to CPPR/Uncertainty at latch opening edge must be subtracted from

Time Borrowed, to enable data launch as soon as data arrives at the data pin of the
latch.

Provided CPPR/Jitter/Phase Shift for all paths reaching D pin are same, it is:

Time Given = Time Borrowed +CPPR – Uncertainty – Jitter

e.g.
Actual Time borrowed = 3.40
Open Edge Uncertainty = 2.10
Open Edge CPPR = 0.3
Time Given to startpoint = 3.40–(2.10-0.3) =1.60

Set timing_use_latch_early_launch_edge global to false to allow CPPR credit when time

borrowing and CPPR are both enabled.
16 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Max Borrow Mode – Late Data with Early Clock
MEM/CKN late launch edge
= 5+0.27=5.270
L1/G opening edge (early)
= 10+0.190 = 10.190
Data Arrival Time = 11.270

Time Borrow
= 11.270 – 10.190 = 1.08

Time Given
= 1.08 – 0.020 (CPPR)= 1.060

L1/G opening edge (late)

= 10+0.360 = 10.360
Late Data launch for RT/D =
10.360 (late) + 1.060 = 11.420

17 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Impact of timing_use_latch_early_launch_edge = false
• Time Borrowed depends on individual paths reaching latch data pin
(CPPR different)
• Time Given a single number for a latch stage
• timing_use_latch_early_launch_edge = false
– All borrowing paths delayed by: X = [Clk(closing edge) – Clk(open edge) – CPPR]
– Launch clock path considered late, capture clock path considered early
– Add X to all path arrival time reaching D pin and take the most critical path

Time Borrowed for path1 = Late Data Arrival Time (AT1) – Clock (open edge)
Time Borrowed for path2 = Late Data Arrival Time (AT2) – Clock (open edge)
Time Given = Max(AT1+X1, AT2+X2, …) – Clock (closing edge)

NOTE: with different clocks, phase shift need to be further accounted for

18 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Limiting Time Borrowing
Limit maximum time borrow by set_max_time_borrow command:

Syntax: set_max_time_borrow <borrow value> <instance pins|cells| clocks>

• Allowed Range : 0 <= <borrow value> <= (Pulse Width – Setup)

• Assertion on clock has higher precedence over assertion on latch instances
• If timing_use_latch_time_borrow=false/set_analysis_mode –timeBorrowing
false, no time borrowing allowed and latches analyzed like a flip-flop
• Smaller of calculated time borrow or <borrow value> is chosen.
If calculated <borrow value> negative, data must be stable before the open
end of the clock, and it will be chosen (for example enable input arrives before
the clock on a gated-clock latch)

19 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Examples - set_max_time_borrow
Disabling time borrowing for all clocks

set_max_time_borrow 0 [all_clocks]
set_max_time_borrow 2.5 \
[get_cells {Latch1 Latch2 Latch3}]

• reset_max_time_borrow clears the limit set by set_max_time_borrow

Syntax: reset_max_time_borrow <List of instance pins|cells| clocks>

reset_max_time_borrow [all_clocks]

20 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Borrow Edge Adjust
• When timing_use_latch_early_launch_edge=false
– Launch Clock Path timed in late mode for SETUP analysis
– Launch clock path timed in early mode for HOLD analysis
– CPPR credit applied
– If Slack > 0 (no time borrowed)
– (C->Q - D->Q) difference added as “Borrow Edge Adjust” in “Required time”
– Can be negative if D->Q > C->Q, slack=0
– Late derate applied to launch clock path
– Arrival Time = Dlate-D->Q, Require Time= Clock_Open_Edge+C->Q
– Slack
= (Clock_open_edge + C->Q ) - (Late Data Arrival -D->Q )
= (Clock_open_edge - Late Data Arrival ) – (C->Q – D->Q)

• When timing_use_latch_early_launch_edge=true (default)

– Launch Clock Path timed in early mode for SETUP analysis
– Launch clock path timed in late mode for HOLD analysis
– No CPPR credit given – assumes no common clock path – which may be false and add
pessimism
21 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Borrow Edge Adjust (Impact of Latch Arcs)
set_global timing_use_latch_early_launch_edge=true set_global timing_use_latch_early_launch_edge=false

22 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Negative Borrow Edge Adjust: (D->Q delay) > (C->Q delay)

23 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 Properties to Query on Time Borrow

Object Type Property Data Type

timing_path is_path_borrowing Boolean
timing_path time_borrowed Float
timing_path time_lent Float
timing_point max_time_borrow Float
24 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Latch Through Mode
D Q D Q D Q
D Q D Q
Flop1 LD3 Flop2
LD1 LD2
CK G CK
G G

CK

Default Violations considers borrowing path a single-segment path to next latch/flop D pin
Optimization based on segment slacks could be pessimistic

To allow a see-through path in cascaded latches, enable Latch Through Mode by setting the globals:
set_global timing_enable_latch_thru_mode true
set_global timing_cppr_propagate_thru_latches true
(calculates CPPR b/w Flop1 to Flop2 instead of segment-by-segment CPPR)

Report timing from Flop1 to Flop2 without path break through latches :
report_timing –from Flop1/Q –to Flop2/D

Prerequisite
For Latch Through Mode to work, Latch must be borrowing from next stage. Otherwise it will have no effect on
timing
25 analysis.
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Sample Latch Through Report

“Latch Window” shows latch

transparency time span

“Adjustment” shows slacks

recovered

26 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Restricting Violation on Time Borrow Path
• Can we have a violation on [DFF to LAT] path instead of [LAT to DFF], with
time borrow enabled ([LAT to DFF] path in inside an IP)

Timing Path : [DFF -> path1 -> [LAT-> path2 -> DFF]]

Solution:
1) Turn off latch borrow mode to switch off time borrow from next stage:

set_global timing_use_latch_time_borrow false

2) Control max borrow time using set_max_time_borrow

27 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Greedy Time Borrow – How to Adjust?

• [DFF to LAT1] consumes full borrow (750ps)

[LAT1 to LAT2] paths starts violating by -130ps

[LAT1 to LAT2] is a short path and inside another IP and cannot be fixed
through ECO.
Timing Path: DFF -> LAT1 -> LAT2 (path unconstrained after latch2)

Solution:
1) Use set_max_time_borrow on LAT1
2) Use set_path_adjust on LAT1 or LAT2 to constrain the path

28 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Fixing Timing Paths Through Latches
• What is the recommendation for timing fixing and optimization for latches?

Solution:
Use latch through mode instead of latch borrow mode setting:
1. set timing_enable_latch_thru_mode true
2. set timing_cppr_propagate_thru_latches true

Another idea is to use PBA (Path Based Analysis). However, PBA also uses
GBA (Group Based Analysis) based time borrow number as seed value -
relatively more pessimistic.

29 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Clock Gating Check and Time Borrowing

D
Clock Gating Cell Q
Flop
CK
D Q A
Enable
B I1
Latch
G

Clock

Will time borrowing be accounted for in clock gating check through Latch ?

30 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

 Clock Gating Check and Time Borrowing (Cont.)
• Two paths for Clock Gating Check at pin I1/A
– through Latch/D -> Latch/Q (time borrow/time given)
– through Latch/G -> Latch/Q (no time borrow/time given)
– Must set timing_use_latch_early_launch_edge to false to choose late delay + derate for latch
launch path

31 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

Support and Feedback

• Support
– Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to interact
with Cadence Customer Support. Visit https://support.cadence.com.

• Feedback
– Email comments, questions, and suggestions to content_feedback@cadence.com.

32 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design
Systems, Inc. All other trademarks are the property of their respective owners.