IC Compiler II（ICC II）后端设计流程——超详细_凳子花

❀的博客-CSDN博客_icc2
blog.csdn.net/qq_42759162/article/details/108461592

Preface
This article combines Chinese and English (learn some proper nouns), and mainly
introduces the main process of ICC II software for back-end design. Before reading, you
need to have a certain understanding of the digital IC design process.

For logic synthesis related knowledge, please check: Synopsys logic synthesis and the use
of DesignCompiler (if you want to know about logic synthesis, you can check this, but
there are more contents)

For the overall process of digital IC design, please check: Some basic concepts and
common sense about digital IC back-end design (if the foundation is not very solid, it is
recommended to read this first)

For the explanation of some terms used in ICC, please check: Full of dry goods – digital
back-end design and ICC tutorial arrangement (it is recommended to pay attention to the
official account, not to advertise, I also found it when I wrote this blog, it is really
comprehensive) (It is recommended to read my blog first to understand the general
process, and then read his to deepen understanding; or when you read my blog, there are
still some proper nouns that do not understand the meaning, you can go to him to find an
explanation, the effect is better good)

This article is similar to the form of notes, integrating some relevant information on the
Internet, and the reference materials are listed in the final Reference, respecting
intellectual property rights.

content

Article directory
Preface
content
Blocks and Design Libraries
Objects
IC Compiler II GUI

Built-In Script Editor

Design Setup
APR Flow - Design & Timing Setup
APR Flow - Floorplan Definition

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 APR Flow - Placement & Optimization
APR Flow - CTS & Optimization
APR Flow - Routing & Optimization
APR Flow - Signoff
Customer Support

Solvnet
Regerence Flow
ICC II介绍
ICC使用步骤
Reference
Appendix

Blocks and Design Libraries

block是所有design数据的载体，给网表创建一个block
针对block的一些命令都是*_block来命名的，比如open_block, save_block
block 包括 design data
design library 包括 block、technology data

read_verilog

open_block save_block

create_lib open_lib save_lib

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门级网表文件（.v文件）

该文件可以用逻辑综合工具（如Design Compiler, DC）来产生，某些部分可以人为手

工修改/编写，在导入ICC中之前，首先需要检查网表的质量，以尽早排除可能造成后
端设计困难的问题，比如浮动输入信号、多驱动、未采用寄存器输入输出、输入到寄
存器、寄存器到寄存器、寄存器到输出、扇入扇出等。这些问题如果及时发现，并在
前端进行改善会比较容易，且非常有利于后端设计的顺利进行。

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Objects

object classes：design, port, cell, pin, net…

get_*

help_attributes

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Attributes of Objects
Each object has attributes, and attributes have values

report_attributes -application [get_selection]

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Application Options (App Options)

place_opt.flow.do_spg controls whether SPG placement is considered

naming convention : a naming convention

SPG : Synopsys Physical Guidence , when synthesizing, use the information of the
back-end physical floor plan to synthesize, highlight some problem information, and
use it for the back-end process

place_opt.flow.do_spg

category.sub_category.option_name

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Finding/Applying Application Options

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report_app_options get_app_options

report_app_options time.* (报道Timing相关的app_options)

report_app_options -non_default (一般都是默认值，该命令可知道哪些进行了修改)

set_app_options -name time.remove_clock_reconvergence_pessimism -value true (设定

app_options)

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IC Compiler II GUI

Built-In Script Editor

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Design Setup

Input IC Compiler are: gate-level netlist, library files, timing constraints.

The output of IC Compiler is layout (the common format is GDSII)

Overview

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 Design Library includes Block, Cell Libraries (ndm format), Technology Library
(ndm format)
Block includes Gate-Level Netlist (gate-level netlist) and some files of Design
constraints

NDM

Timing View can be understood as db, including timing information and power
consumption information
The design view is equivalent to doing design, such as block, the design itself has the
results of winding and place
frame view is the same as lef

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 lef file is place and route According to the file format of the cell geometric
information library used, the layout and routing tool will determine how to layout,
how to route, and how to generate vias based on the information in the LEF file.

LEF:

(Library exchange format), called the library exchange format, which describes the physical
properties of the library unit, including port location, layer definition and via definition. It
abstracts the underlying geometric details of the cell, providing enough information to allow
the router to make cell connections without revisions to internal cell constraints. It contains
the technical information of the process, such as the number of layers of wiring, the
minimum line width, the minimum distance between lines, and the size of each selected cell,
BLOCK, PAD and the actual position of the pin. The information of cell and PAD is given
by the LEF file provided by the manufacturer, and the LEF file description of the
customized BLOCK is generated after ABSTRACT, as long as the two LEF files are
integrated.

For other file format descriptions, please refer to: Common file format descriptions
in back-end design

block library

The block library can actually be understood as ndm

design view: the default view
frame view: limited A physical view that contains only the information needed to
perform placing and routing a block as an instance to an instance port: block
outline, pins, via areas, and routing blocks

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 The abstract view is more important. It is a simplified version of the design view.
The abstract view is used when top is implemented, and the physical information of
the interface and the physical information on the clock tree are extracted.

IC Compiler II Library Manager

ndm is generated using an ICC II Library Manager

For some standard units/memory/IP/IO used in all designs, you need to know
Timing information (.db file)/physical information (.frame/LEF/GDS)/technical
files
Generate NDM through ICC II Library Manager, NDM contains logic/physical
information, and then use it in ICC II

Library Manager(icc2_lm_shell) Flow

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Library Prep-icc2_lm_shell

a simple script

create_workspace 需要指定一个名字以及需要的tech file

read_db read_lef

check_workspace

commit_workspace 保存ndm

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APR Flow - Design & Timing Setup

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 automatic place and route ：布局就是在版图上给单元、宏模块等分配物理位置，使
得单元、宏模块等部件互不重叠。该分配需要根据用户给出的特定约束来对代价函数
进行优化。布局之后,单元和引脚的确切位置己经确定,所需的互联也已经确定。为布
线预留的区域称为布线区。布线必须在布线区内进行,要遵循布线规则,不能引起布线
的规则违反。

中文名

自动布局布线

外文名

Automatic Placement and Routing, APR

有了ndm就可以进行design & timing setup

create a design library

load the netlist and power intent(UPF)

apply the floorplan

load the scan chain definitions(scan-DEF)

perform MCMM setup

apply timing and optimization controls

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 如今的集成电路（Integrated Circuit，IC）设计往往要求芯片包含多个工作模式，并
且在不同工艺角（corner）下能正常工作。工艺角和工作模式的增加，无疑使时序收
敛面临极大挑战。
MCMM（Multicorner-Multimode）技术: 多工艺角多工作模式
corner:

不同的晶片和不同的批次之间，MOSFETs参数的变化范围比较大。为减轻设计困难
度，需要将器件性能限制在某个范围内，并报废超出这个范围的芯片，来严格控制预
期的参数变化。工艺角即为这个性能范围。

5-corner model：

5-corner model有5个corners：TT，FF，SS，FS，SF。前后两个字符分别对应NMOS
和PMOS。其中TT是指typical corner。Typical表示晶体管饱和电流的平均值。单一器
件所测的结果是呈正态分布的。均值为TT，最小最大限制为SS和FF。饱和电流
（Isat）大的器件，阈值电压小（LVT），运行速度快（F）。饱和电流（Isat）小的
器件，阈值电压大（HVT），运行速度慢（S）。

不同的工艺不同的device对应的sigma值不同。如果NMOS和PMOS的性能与Typical的
偏差在3sigma时，也能满足设计需求，则此corner芯片为3SS或者3FF corner 芯片。

DEF：

DEF: (Design exchange format), called design exchange format, is a file in ASCII format,
which describes the actual design, lists the library units and their locations and connection
relationships, and uses DEF to communicate between different design systems Transfer
designs while keeping the content of the design intact. DEF is not the same as GDSII which
only conveys geometric information. It can pass the logical and physical information of the
design to the place and route tools. Logical information includes logical connection
relationships (represented by netlists), grouping information, and physical constraints.
Physical information includes layout planning, layout location and orientation, and routing
geometry data.

Create a “Container”: The Design Library

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 Create of design library:
Specify technology and some cell libraries (cell is ndm)
The default library is stored in memory

lappend search_path /x/y/libs

create_libs ORCA.dlib \

-use_technology_lib abc14_9m_tech.ndm \

-ref_libs {

abc14_9m_tech.ndm

abc14_hvt_std.ndm abc14_svt_std.ndm abc14_lvt_std.ndm

abc14_srams.ndm abc14_ip.ndm

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Read the Netlist and Create a Design

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 Read netlist to generate block

lappend search_path ./netlist

read_verilog -top ORCA ORCA.v

link_block

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Multiple Modes and Multiple Corners

The current chip will operate in many modes and different corners
multiple modes

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 standby mode, test mode, low power mode, high performance mode, normal functional
mode

multiple corners

Hi-T Slow, Lo-T Slow, Lo-T Fast, Hi-T Fast, Max Leakage

more information please check: Multi-mode multi-angle MCMM (Mulit-Corner

Mult-Mode) in digital IC design

Concurrent MCMM Optimization

Concurrent: parallelism, simultaneous access, concurrency, parallelism

Because of the different application scenarios, these modes and corners are
combined to form a scenario, that is, scenarios, scenarios

FUNC_SLOW Scenario = FUNC Mode + SLOW Corner

IC can optimize under different scenarios at the same time, improving each conflict
in one scenario, while trying not to cause/increase conflicts in another scenario
violation: illegal, violation

Mode, Corner and Scenario Setup

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 First define mode and corner, and then combine mode and corner to form scenarios

create_mode M1

create_mode M2

create_corner C1; // Common corner to both modes

create_scenario -mode M1 -corner C1 -name M1_C1

create_scenario -mode M2 -corner C1 -name M2_C1

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Loading Constraints

After getting the scenario, you need to read in some constraint files
populate: fill, migrate, emigrate, live in, live in

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current_scenario M1_C1 current_scenario M2_C1

read_sdc C1_corner.sdc read_sdc M2_mode.sdc

read_sdc M1_mode.sdc read_sdc M2_C1_scenario.sdc

read_sdc M1_C1_scenario.sdc

read_sdc global_constraints.sdc

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Defining PVT Directly - Recommended

Specify the corresponding process/voltage/temperature for each scenario

It is recommended to use this direct assignment method

set_process_number 0.99

set_voltage 0.75 -object_list VDD

set_voltage 0.95 -object_list VDDH

set_temperature 125

Specify TLUplus Parasitic RC Models

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 Bring in the model of parasitic parameter extraction
For each corner, read the TLUplus file corresponding to the corner
TLUplus can be read from the ndm in the previous tech library, or it can be specified
in the subsequent design library

#if the TLUplus models have not been loaded into a technology library, they can

#be loaded into the design library:

#read_parasitic_tech -tlup $TLUPLUS_MAX_FILE -name maxLTU

#read_parasitic_tech -tlup $TLUPLUS_MIN_FILE -name minTLU

set_parasitic_parameters -corner c_slow -library $(techlib) -early_spec maxTLU -

late_spec maxTLU

set_parasitic_parameters -corner c_fast -library $(techlib) -early_spec minTLU -

late_spec minTLU

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 tluplus file

Parasitic RC lookup table (a binary table format that stores RC coefficients), ICC uses the
network geometry and this file to calculate the interconnect resistance capacitance. TLUPlus
models enable accurate RC extraction results by including width, space, density and
temperature effects on resistivity.

If there is no tluplus file, it can be converted to tluplus by the .itf given by Foundry. The full
name of the .itf file is Interconnect Technology Format

The itf file is provided by foundry to generate tluplus files for use in the ICC process. Use
Synopsys' Star-RCXT, just use this command in the shell:

grdgenxo -itf2TLUPlus -i -o <TLU+ file>

Controlling Scenario Analysis / Optimization

simultaneously: at the same time

create_scenario

set_scenario_status

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APR Flow - Floorplan Definition

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Floorplanning Overview

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 Defining

defines size and shape

Shape and location of the voltage domain
Macro position
Location of I/O pins
To avoid congestion, some blockages of standard units may be used
Generate Power Network PNS

write floor

Create the Initial Floorplan

initialize_floorplan -shape U

Place Macros and Standard Cells

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 coarse: rough
Put both macro and standard units in
Before running place opt, fix the placement of all macros

create_placement -floorplan [-congestion]

set_fixed_objects [get_flat_cells -filter "is_hard_macro"]在place_opt之前要把

hard_macro fix住

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Place I/O Pins

After placing the macro, you need to place the I/O Pins
Usually when the macro is placed, it will be placed next to the block, but sometimes
it will block the macro
When arranging pins, you need to pay attention. Sometimes there will be some
interactions between blocks, so there may be constraints on the placement of pin
blocks; or there are some special requirements for the placement of special pins,
such as signal pins, clocks, and differential signal pins. , if required, you need to
read it in before placing the pins, and use place_pins -self to place all the pins in the
correct position.

set_block_pin_constraints -self -allowed_layers "M3 M4" -sides "1 2 3" | -

exclude_sides "4 5 6"

set_individual_pin_constraints -ports ...

place_pins -self

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Power Planning Challenges

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 Build a power network

Pattern_Based Power Network Synthesis

topology: topology
no fixed coordinates: no fixed coordinates
coordinate: n: coordinate, set; v: collocation, coordination
First define a region for it
The structure of the define power grid: hierarchy, line width, distance between lines
把pattern放到PG region中，同时可也以apply到voltage area 或者是bounds，需要指
定打哪些net，比如VDD、VSS等；这样做的好处是，全程都不会有固定坐标的方
式，当floorplan后续有一些变化时，就很灵活，不需要手动改这些数值
compile power network

Write out the Floorplan for ICC II/DC-G

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 把floorplan信息写下来，如果需要重新跑一下ICC，可以引用之前存下来的信息
如果送到前端综合的话，是不需要包含标准单元的placement的，DC在综合的时候会
重新考虑macro的摆放

write_floorplan -output ORCA_TOP.fp

write_floorplan -format icc -output ORCA_TOP.fp.dc -net_types {power ground} -

include_physical_status {fixed locked}

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APR Flow - Placement & Optimization

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Key Steps of the Placement Phase

Design and Flow Requirement Setup Steps

指定scenario去优化
选择是否打开SPG Flow，SPG就是之前DC-G综合之后产生一个初始位置信息，ICC
II可以直接使用这个信息做下面的优化
remove掉不需要的ideal networks
指定特定类型的library cell去使用
选择是否优化leakage或者dynamic或者leakage+dynamic的total优化
SPG：synopsys physical guidence

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Congestion-Focused Setup Steps

density: 密度
QoR主要分为三部分：Congestion/Timing/Power
Congestion
跑完place_opt后先分析congestion和cell/pin density
如果有拥堵问题的话，可以使用以下方法去解决congestion
Timing
Power/Area

The Five Stages of place_opt

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 five stages : initial_place/initial_drc/initial_opto/final_place/final_opto

Placement and Logic Optimization: place_opt

place_opt默认会直接跑完五个阶段
可以使用-from/-to控制阶段，可以提高效率
可以通过app options控制：congestion/timing等

Recommended place_opt Exploration Flow

Example Script

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open_lib design.dlib

open_block floorplan

#Place setup

remove_ideal_network -all

set_lib_cell_purpose -include none [get_lib_cells "*/*BUF_X64* */*REG_ulvt*"]

set_app_options -list [opt.power.mode none | leakage | dynamic | total]

#Apply Place configuration steps, as needed

set_scenario_set_scenario_status * -active false

set_scenario_status <list_of_placement_scenarios> -active true

set_scenario_status *corner_FAST -setup false

set_scenario_status mode_TEST* -leakage_power false

#Enable SPG, if applicable:

set_app_options -list {place_opt.flow.do_spg true}

place_opt

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APR Flow - CTS & Optimization

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The definition of CTS

在大规模集成电路中，大部分时序元件的数据传输是由时钟同步控制的时钟频率决定
了数据处理和传输的速度，时钟频率是电路性能的最主要的标志。在集成电路进入深
亚微米阶段，决定时钟频率的主要因素有两个，一是组合逻辑部分的 最长电路延
时 ，二是同步元件内的 时钟偏斜(clock skew) ,随着晶体管尺寸的减小，组合逻辑电路
的开关速度不断提高，时钟偏斜成为影响电路性能的制约因素。时钟树综合的主要目
的是减小时钟偏斜。

以一个时钟域为例，一个时钟源点(source )最终要扇出到很多寄存器的时钟端(sink)，
从时钟源扇出很大，负载很大，时钟源是无法驱动后面如此之多的负载的。这样就需
要一个时钟树结构，通过一级一级的buffer去驱动最终的叶子结点(寄存器)。

Clock Tree Synthesis Goal and Flows

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 CTS的目的：
建立时钟树缓冲结构
给时钟网络布线
优化数据路径逻辑以建立和保持时序以及DRC
支持两种CTS流
典型的CTS流：首先做CTS，然后数据路径优化
并行时钟、数据流：CTS和数据路径优化并行执行
建议用于时序关键型设计

Comparing Classic CTS versus CCD

Classic CTS不看data path，只看clk入点到每个reg点之间的tree是不是平的，减少

skew偏差
优化时data path是一个untouched状态
CCD优化时可能会动到clock tree，而Classic CTS不会

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Clock Tree Balancing Setup

# 设定clock tree balance

set_clock_balance_points

# 指定期望的延时以及相互之间的偏差
set_clock_tree_options

# 控制CTS选择哪种cell

set_lib_cell_purpose -include cts $cts_cells

set_dont_touch $cts_cells false

create_clock_balance_group

derive_clock_balance_constraints -slack_less_than -0.3

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Non-Default Rules

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Defining/Applying NDR

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create_routing_rule 2xs_2xW_CLK_RULE -width {M1 0.11 M2 0.11 M3 0.14 M4 0.14 M5
0.14}\

-spacings {M1 0.4 M2 0.4 M3 0.48 M4 0.48 M5 1.1}

-cuts {

{VIA3 {Vrect 1}}\

... \

{VIA5 {Vrect 1}}\

set_clock_routing_rules -rule 2xs_2xW_CLK_RULE -min_routing_layer M4 -

max_routing_layer M5

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Defining CTS-Specific DRC Values

set_max_transition <value> -clock_path [all_clocks] (default: 0.5ns)

set_max_capacitance <value> -clock_path [all_clocks] (default: 0.6pF)

set_max_transition 0.2 -clock_path -scenarios "S1 S4" [get_clocks SYS_CLK]

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CTS Execution

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clock_opt

#CCD enabled

clock_opt.flow.enable_ccd

#four stages of clock_opt

bulid_clock -> route_clock -> final_optp -> global_route_opt(optional)

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Analyzing CTS Results: Clock QoR Report

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report_clock_qor [-type area | balance_groups | drc_violators | latency |
local_skew \

| power | robustness | structure | summary] \

[-histogram_type latency | transition | level |...]

[-modes ...] [-corners ...]...

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Analyzing CTS Results: Clock Timing Report

report_clock_timing -type summary | transition | latency | ...

-modes {m1 m2}

-corners {c1 c2}...

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Example Script

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37/58
open_lib design.dlib

open_block place

#CTS setup

source clock_tree_balance.tcl

source clock_routing_tules.tcl

source clock_constraints.tcl

#Apply CTS configuration steps, as needed

set_scenario_status -active true [all_scenarios]

set_scenario_status {s2 s4} -hold true

set_app_options -name clock_opt.hold.effort -value high

set_app_options -name cts.compile.enable_global_route -value true

set_app_options -name opt.common.allow_physical_feedthrough -value true

#Enable CCD, if applicable:

set_app_options -name clock_opt.flow.enbale_ccd -value true

clock_opt

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APR Flow - Routing & Optimization

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Routing Phase Goal

routing阶段的目的是：
以最小的物理DRC违规路由所有信号网
优化定时、DRC和电源的数据路径逻辑
可选择执行后路CTO或CCD

Recommended Routing Flow

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route_auto

#Routing performs

Global Routing -> Track Assignment -> Detail Routing

route_opt

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并行优化
时序和最大转换/最大电容（默认）
时钟树、电源（可选择）
可选地使用PrimeTime延迟计算和StarRC提取

Check Zroute DRC Violations

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check_routes

Example Script

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open_lib design.dlib

open_block cts

#route setup

source antenna_rules.tcl

set_app_options -list {

route.global.timing_driven true

route.track.timing_driven true

route.detail.timing_driven true

set_app_options -name time.si_enable_analysis -value true

#Apply route configuration steps, as needed

set_scenario_status -active true [all_scenarios]

set_scenario_status {s2 s4} -hold true

#Enable CCD, if applicable:

set_app_options -name route_opt.flow.enable_ccd -value true

route_auto

route_opt

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APR Flow - Signoff

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Signoff

主要是做一些Timing ECO或者一些Functional ECO, 就是进行DRC和LVS物理验证。

ASIC设计流程中 验证测试完成后的确认叫sign-off（字面意思就是负责人签字）包括
前端signoff和后端signoff 后端signoff之后就是tape-out

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 1、什么是signoff？
signoff，签发。

后端所说的signoff，是指将设计数据交给芯片制造厂商生产之前，对设计数据进行复
检，确认设计数据达到交付标准，这些检查和确认统称为signoff。

2、signoff的主要方向

timing signoff 静态时序验证

PA signoff 电源完整性分析

PV signoff 物理验证

RV signoff 可靠性验证

FM/CLP signoff 形式验证和低功耗验证

3、signoff要点

timing：setup check 建立时间检查——hold check 保持时间检查——drv check 最大传

输时间检查和最大电容检查——SI check 信号一致性检查；

PA signoff：关注芯片功耗，静态和动态IR降，电荷迁移等；
PV signoff：关注芯片是否满足工艺设计规则，物理设计与逻辑网表的一致性；

RV signoff：关注ESD，latchup，ERC等检查；

FM signoff：关注最终输出的逻辑网表与最初输入的逻辑网表之间的一致性；

CLP signoff：关注在低功耗设计中引入的特殊单元，电源域划分及组成单元的正确
性；

4、通常设计人员所说的第一次signoff指的是代码的冻结freeze，freeze code后，后续
所有的代码修改均需提交patch进行审核。

Prime Time Signoff-driven Physically Aware ECO Flow

Timing ECO

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 PrimeTime inputs:

Netlist(Verilog)
Timing constraints(SDC)
Power Intent(UDF)
Layout(NDM or DEF+Tcl)
RC Parasitics with coordinates(SPEF, GPD)
Standard cell spacing rules(Encrypted Tcl)
Logic dbs
Tech Info(CLIB or LEF)
Physical libraries(CLIB or LEF)

PrimeTime ouput:

ASCII ECO file with coordinates

时序约束文件（.sdc文件）

该文件可以由DC工具导出，并人工进行修改，以使其满足设计要求，约束要合理，
不能过约束，否则后端软件可能无法达到要求。

Function ECO Flow

在design设计可能会出现bug，后仿时也会出现一些问题，我们要做一些修正，不会
从综合开始重新开始，经常使用ECO来解决
先比较，把改动的东西写出来；然后apply change，把eco cell摆放进去；最后做
一个eco route

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#Perform ECO comparison

eco_netlist -by_verilog_file ECO_netlist.v -write_changes ECO_changes.tcl

#Apply ECO changes and place

source ECO_changes.tcl

connect_pg_net

place_eco_cells -cel_changed_cells

#ECO routing and post-route optimization

route_eco -max_detail_wires true -utilize_dangling_wires true -open_net_driven

true \

-reroute modified_nets_first_then_others

route_opt

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Standard Cell Fillers and Metal Fill

标准单元填充以及金属填充

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 Boundary cell insertion
place_opt
clock_opt
Initial Route(route_auto)
Post-route Opt(route_opt)
Filler cell Insertion
Add Metal Fill

Filler Insertion & Removal

Filler cell insertion

#Insert filler cells. First cells with metal, then without

#Should be sorted from largest to smallest

set FILLER_CELL_METAL "saed32/FILL128 saed32/FILL64 ... saed32/FILL2 saed32/FILL1"

create_stdcell_fillers -lib_cells $FILLER_CELL_METAL

connect_pg_net

remove_stdcell_fillers_with_violation

create_stdcell_fillers -lib_cells $FILLER_CELL_NO_METAL

connect_pg_net

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 Filler cell removal

remove_cells [get_cells -hierarchical -filter design_type==filler]

In-Design Signoff DRC Checking and Fixing

eliminate: 消除
不需要流式输出设计来运行DRC

Signoff DRC using IC Validator

Metal Fill Insertion

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Customer Support

Solvnet

Regerence Flow

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ICC II介绍

IC Compiler，简称ICC，是Synopsys新一代布局布线系统（Astro是前一代布局布线系
统），通过将物理综合扩展到整个布局和布线过程以及Sign off驱动的设计收敛，来
保证卓越的质量并缩短设计时间。上一代解决方案由于布局、时钟树和布线独立运
行，有其局限性。IC Compiler的扩展物理综合(XPS)技术突破了这一局限，将物理综
合扩展到了整个布局和布线过程。IC Compiler采用基于TCL的统一架构，实现了创新
并利用了Synopsys的若干最为优秀的核心技术。作为一套完整的布局布线设计系统，
它包括了实现下一代设计所必需的一切功能，如物理综合、布局、布线、时序、信号
完整性(Signal Integrity, SI)优化、低功耗、可测性设计(Design For Test, DFT)和良率优
化。新版ICC运行时间更快、容量更大、多角/多模优化(MCMM)更加智能、而且具有
改进的可预测性，可显著提高设计人员的生产效率。同时，新版本还推出了支持45
nm、32 nm技术的物理设计。IC Compiler正成为越来越多市场领先的IC设计公司在各
种应用和广泛硅技术中的理想选择。新版的重大技术创新将为加速其广泛应用起到重
要作用。IC Compiler引入了用于快速运行模式的新技术，在保证原有质量的情况下使
运行时间缩短了35%。新版增加了集成的、层次化的设计规划的早期介入，有助于用
户高效处理一亿门级的设计。提高生产能效的另一个关键在于物理可行性流程，它能
够使用户迅速生成和分析多次试验布局，以确定具体实现的最佳起始值。

ICC命令集
请查看：ICC 命令集

==注：==该文只是总结了ICC的一些命令，但是没有对应的解释，各命令具体含义，请在
ICC命令行man一下进行查阅。

多级物理层次

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 不支持多级物理层次的话就得并行，支持的话就可以包含进去

可扩展Timer

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 Timer可进行时序运行
ICCII是基于mode而不是scenario，一个mode对应的库有不同的电压/温
度/process，这样就可以对不同的PVT进行插值，从而增加更多的灵活性

并行优化

preroute optimization

首先是place，place之后有一个early clock，即做一个早期的CTS，目的是在place阶
段考虑到clock对于绕线以及clock cell/clock buffer面积的影响；如果对IC进行优化的
话，因为无法知道ICG的slack，因为你没有做tree，即early clock就是做一个初期的
tree来预估ICG的timing，然后进行优化；故在place阶段需要把early clock进行使
能，使它在做完timing之后时间都很match
place之后的timing可以和cts之后的timing一致性做的非常好

主要特点

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Fusion with redhawk

Fusion with StarRC & PT/PX

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Fusion with ICV

other fusion

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PT StarRC直接读取ICCII Database

ICC使用步骤
ICC使用----ICC 1 Lab Guide学习笔记

Reference
新思在线课程：IC Compiler

极术干货|Mount-新一代布局总线系统IC Compiler II 初识（PPT下载+视频回放）

process corner工艺角什么是itf文件？什么是TLUplus文件？

芯片Timing sign-off Corner理解

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后端signoff含义

关于数字IC后端设计的一些基础概念与常识

干货满满–数字后端设计及ICC教程整理

IC Compiler简介

ICC后端设计准备-1.数据准备

Appendix
Signoff (electronic design automation)

Signoff (electronic design automation)

In the automated design of integrated circuits, signoff (also written as sign-off) checks
is the collective name given to a series of verification steps that the design must pass
before it can be taped out. This implies an iterative process involving incremental fixes
across the board using one or more check types, and then retesting the design. There are
two types of sign-off’s: front-end sign-off and back-end sign-off. After back-end sign-off
the chip goes to fabrication. After listing out all the features in the specification, the
verification engineer will write coverage for those features to identify bugs, and send back
the RTL design to the designer. Bugs, or defects, can include issues like missing features
(comparing the layout to the specification), errors in design (typo and functional errors),
etc. When the coverage reaches a maximum% then the verification team will sign it off. By
using a methodology like UVM, OVM, or VMM, the verification team develops a reusable
environment. Nowadays, UVM is more popular than others.

Check types
Signoff checks have become more complex as VLSI designs approach 22nm and below
process nodes, because of the increased impact of previously ignored (or more crudely
approximated) second-order effects. There are several categories of signoff checks.

Design rule checking (DRC) – Also sometimes known as geometric verification, this
involves verifying if the design can be reliably manufactured given current
photolithography limitations. In advanced process nodes, DFM rules are upgraded
from optional (for better yield) to required.
Layout Versus Schematic (LVS) – Also known as schematic verification, this is used
to verify that the placement and routing of the standard cells in the design has not
altered the functionality of the constructed circuit.
Formal verification – Here, the logical functionality of the post-layout netlist
(including any layout-driven optimization) is verified against the pre-layout, post-
synthesis netlist.

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 Voltage drop analysis – Also known as IR-drop analysis, this check verifies if the
power grid is strong enough to ensure that the voltage representing the binary high
value never dips lower than a set margin (below which the circuit will not function
correctly or reliably) due to the combined switching of millions of transistors.
Signal integrity analysis – Here, noise due to crosstalk and other issues is analyzed,
and its effect on circuit functionality is checked to ensure that capacitive glitches are
not large enough to cross the threshold voltage of gates along the data path.
Static timing analysis (STA) – Slowly being superseded by statistical static timing
analysis (SSTA), STA is used to verify if all the logic data paths in the design can
work at the intended clock frequency, especially under the effects of on-chip
variation. STA is run as a replacement for SPICE, because SPICE simulation’s
runtime makes it infeasible for full-chip analysis modern designs.
Electromigration lifetime checks – To ensure a minimum lifetime of operation at the
intended clock frequency without the circuit succumbing to electromigration.
Functional Static Sign-off checks – which use search and analysis techniques to
check for design failures under all possible test cases; functional static sign-off
domains include clock domain crossing, reset domain crossing and X-propagation.

Tools

A small subset of tools are classified as “golden” or signoff-quality. Categorizing a tool as

signoff-quality without vendor-bias is a matter of trial and error, since the accuracy of the
tool can only be determined after the design has been fabricated. So, one of the metrics
that is in use (and often touted by the tool manufacturer/vendor) is the number of
successful tapeouts enabled by the tool in question. It has been argued that this metric is
insufficient, ill-defined, and irrelevant for certain tools, especially tools that play only a
part in the full flow.[1]

While vendors often embellish the ease of end-to-end (typically RTL to GDS for ASICs,
and RTL to timing closure for FPGAs) execution through their respective tool suite, most
semiconductor design companies use a combination of tools from various vendors (often
called “best of breed” tools) in order to minimize correlation errors pre- and post-silicon.
[2] Since independent tool evaluation is expensive (single licenses for design tools from
major vendors like Synopsys and Cadence may cost tens or hundreds of thousands of
dollars) and a risky proposition (if the failed evaluation is done on a production design,
resulting in a time to market delay), it is feasible only for the largest design companies
(like Intel, IBM, Freescale, and TI). As a value add, several semiconductor foundries now
provide pre-evaluated reference/recommended methodologies (sometimes referred to as
“RM” flows) which includes a list of recommended tools, versions, and scripts to move
data from one tool to another and automate the entire process.[3]

This list of vendors and tools is meant to be representative and is not exhaustive:

DRC/LVS - Mentor HyperLynx DRC Free/Gold, Mentor Calibre, Magma Quartz,

Synopsys Hercules, Cadence Assura
Voltage drop analysis - Cadence Voltus, Apache Redhawk, Magma Quartz Rail

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 Signal integrity analysis - Cadence CeltIC (crosstalk noise), Cadence Tempus Timing
Signoff Solution, Synopsys PrimeTime SI (crosstalk delay/noise), Extreme-DA
GoldTime SI (crosstalk delay/noise)
Static timing analysis - Synopsys PrimeTime , Magma Quartz SSTA , Cadence ETS ,
Cadence Tempus Timing Signoff Solution , Extreme-DA GoldTime

References

1. ^ DeepChip - SNUG survey of physical verification tools .

2. ^ TSMC's sign-off flow

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