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Synthesis
Physical Optimization
Post-CTS Optimization
Post-Route Optimization
Final Layout
Synthesis
Post-Route Optimization
Final Layout
OCV ± 10%
A B C
D ≈ clock period
D
2T … 5T
gate offsets CG
skew
CG
offset
D < T - skew Clock gates are supposed to have a very big skew
clock (T)
10,000 FFs
? “Skew “does not include
interclock skew
skew
Are all FFs
“balanced”?
Clk-C Clk-D
1,000 FFs
AOI2
D 2,000 FFs
180nm, σ = 7% of T
65nm, σ = 27% of T
45nm, σ = 50% of T
60%
with ocv
inter-clock
50%
reg-to-cg
reg-to-reg
40%
30%
20%
10%
0%
180nm 130nm 65nm 45nm
Synthesis
Initial Placement
“Ideal clocks”
Big decisions about chip
speed vs. area vs. power
Physical Optimization made here using ideal clocks
Post-CTS Optimization
Post-Route Optimization
Final Layout
Synthesis
Pretend clocks
“Ideal clocks”
Initial Placement
Real clocks
“Propagated clocks”
Routing
Post-Route Optimization
Final Layout
clock T clock T
Extend physical
optimization into
the clocks
L C
skew
Gmax Gmax
More
degrees of
freedom
Gmax < T - skew L + Gmax < T + C
clock
? ?
slack
clock
Looping Chain
IO Chain
critical path
slack
Logic delay
11 13 8
Delay 11+9+19+8+13
= = 12
Stage 5
9 19
15 11
Delay 15+16+11
= = 14
Stage 3
16
critical chain
Final Layout
Reduced IR-drop
– Clocks are not balanced!
Reduced power
– Clock buffers are only used where it is necessary for timing
Global routing
Placement – Ability to export “route guides”
Verilog Placed SDC
netlist DEF Physical Optimization
Phys. Opt. – Timing-driven incremental placement
– Timing-driven high-fanout net buffering
– Cell sizing and logic transformations
CTS RUBIX™ – Legalization
Clocks
Post-CTS Opt.
– Comprehensive skew group support
Verilog Placed
(can mix and overlap with timing windows
netlist DEF
based CTS)
Routing
Multi-voltage
– Clock buffering and net buffering across
voltage islands
PRO
Timing driven scan-chain
reordering
– Setup and hold aware
GDSII