Galaxy Constraint Analyzer™

Advanced Constraint
Debugging

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 Agenda

Galaxy Constraint Analyzer

• The Constraints Challenges
• Look-ahead Technology
• Values
• Main Features

Block-to-Top Consistency Checking

Analyze Constraints Changes

Customizing Rules

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 Galaxy Constraint Analyzer
Timing Constraints Challenges

Up to 100M 100s of • Frequent design and

instances clocks constraint reuse

• 3rd party IP

• Global design teams

Multiple
>100 Signoff
scenarios
voltage • No change to tapeout
domains
timeline
Source: M.Bohr, Intel 2008; Wikipedia, TSMC

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 Galaxy Constraint Analyzer
Impact of Constraint Problems

Timing Constraint Issue Impact

Incorrect application of false

Non-functional silicon
path after optimization

Conflicting constraints
Tapeout delayed!
across hierarchy boundaries

Multiple days of iterations

Incorrect definition of a
involving clock tree
generated clock
synthesis

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 Galaxy Constraint Analyzer
Look-ahead Technology
• Constraint rule checking to find
missing, incorrect, conflicting or
Constraint Analysis & Debug

Synthesis unnecessary constraints

(DC) • Intuitive root cause analysis of errors
• Fast cleanup, improved productivity
P&R
(ICC) Constraint Cleanup
Without
Signoff GCA
(PT) Synthesis Place & Route Signoff
Synthesis P&R

Constraint Analyzer in GCA Up to 10X

Flow Faster Cleanup
Galaxy Design Flow
Turn Around Time
Source: Synopsys Webinar, April 2010

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 Galaxy Constraint Analyzer
Values

Faster Path to Tapeout

• Fast learning curve, very intuitive environment
• Very fast runtime
Better QoR From Implementation tools
• Avoids implementation runs with bad constraints
• Constraints propagation consistent with PrimeTime
Facilitates Team Collaboration
• Helps with constraint handoff
• Validate 3rd party IPs constraints

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 Galaxy Constraint Analyzer
Built-In Rule Categories

Boundary Conditions
CAP_xxxx – capacitance values
DRV_xxxx – drive constraints
EXD_xxxx – external delays
Exceptions and Case Analysis
CAS_xxxx – case analysis
EXC_xxxx – timing exceptions
Clocks
CLK_xxxx – clock properties
CGR_xxxx _ clock groups
CNL_xxxx – network latencies
CSL_xxxx – clock source latencies
CTR_xxxx – clock transitions
UNC_xxxx – clock uncertainties
General
DES_xxxx – design constraints
LOOP_xxxx – timing loops
NTL_xxxx – netlist
UNT_xxxx – library units

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 Focusing the Debugging Effort
Specialized Debugging Commands

Traces propagation of Identifies sources of

different clock senses a case value
Displays generated Constant on a pin
clocks source Shows forward
latency and Clock and case propagation
traversal propagation value of constants
propagation from a pin

Identifies Data path Unclocked Identifies

constraints causes for
which are propagation register pins unclocked pins
blocking data in the design
propagation in a
region of the design

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 Galaxy Constraint Analyzer
GUI Environment Snapshot

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 Galaxy Constraint Analyzer
A Customer Example

Challenges Galaxy Constraint Analyzer

•Design and Phase •Galaxy Constraint Analyzer

Runtime <50 minutes
15 Million Instances
Memory <25 Gb
Clock Tree Synthesis
Identified inconsistencies in
Gclocks sequential depths
•Issue
Significant clock latencies
Not able to build clock tree

•Impact Saved Multiple Days

Several days of back and of Debugging Efforts
force between STA and CTS
teams

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 Agenda

Galaxy Constraint Analyzer

Block-to-Top Consistency Checking

• Principle
• Use Model
• Debugging Examples

Analyze Constraints Changes

Customizing Rules

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 Block-to-Top Consistency Checking
Introduction

• Most designs include:

 3rd party IPs
 Blocks from previous projects
 Blocks designed by a different group in the
company

• How can you verify that the blocks have

the correct constraints propagating
through the top level logic to the block?

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 Block-to-Top Consistency Checking
Principle
Chip_Top
Output
Input USB_core Delay?
Delay? MCP?

Clock
Signals?

• Consistency checking  Clocks  Case analysis settings

between top and block  Exceptions  Disable timing
level constraints
• Particularly valuable  Clock sense  Input delays
for checking IP  Clock gating  Output delays
constraint integration commands

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 Block-to-Top Consistency Checking
B2T Rule Categories

Rule Type of Problems Flagged

B2T_CAS_xxxx Issues related to case and constant values

B2T_CLK_xxxx Issues related to clock definitions

B2T_DIS_xxxx Issues related to disabled objects

B2T_EXC_xxxx Issues related to exceptions

B2T_EXD_xxxx Issues related to input or output delays

B2T_OPC_xxxx Issues related to operating conditions

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 Block-to-Top Consistency Checking
Behavioral Constraint Checking

set_multicycle_path 2 \
–from [get_ports in1]

in1

Endpoint sees a MCP 2

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 Block-to-Top Consistency Checking
Behavioral Constraint Checking

set_case_analysis 1 \ set_multicycle_path 2
[get_ports top1] –through [get_pins block/in1]
1
top1

top2 1 in1 1

top3
1

set_case_analysis 1 \
[get_ports top3]

Endpoint DOES NOT see a

MCP 2 -> VIOLATION

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 Block-To-Top Consistency Checking
Recommended Flow

Top-Level rule Block-Level rule Compare block and

checking checking top level constraints

• Link top design • Link block design • Run constraint

• Read top • Read block comparison
constraints constraints between top and
• Analyze_design • Analyze_design block
• Fix any • Fix any • Constraints
constraint issue constraint issue needs to be
checked for
completeness
before this stage

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 Block-To-Top Consistency Checking
Sample Script
gca_shell
read_verilog ${TOP_DIR}/design/TopLevel.v
read_verilog ${TOP_DIR}/design/BlockLevel.v

link_design Top
link_design –add Block

current_design Top
source ${CONSTRAINTS}/TopLevel.sdc –echo
analyze_design –verbose

current_design Block
source ${CONSTRAINTS}/Block.sdc –echo
analyze_design -verbose

current_design TopLevel
compare_block_to_top -block_design [get_designs Block] –verbose

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 Block-to-Top Consistency Checking
Debugging a Clock Mismatch

• Galaxy Constraint Analyzer easily helps

you find clock definition mismatches
– Reported as a B2T_CLK_0003
– Multiple ways to find where the issue comes
from (both textually and graphically)
– Easy way to find what object in the design are
affected

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 Block-to-Top Consistency Checking
Debugging B2T Violations

Both Top and Block

constraints causing
the issue

Selected
Violation

2 different suggested
commands to get more info

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 Block-to-Top Consistency Checking
Dual SDC Viewer
• B2T violations involve two different sets of
constraints.
• Dual SDC browser allows you to compare them
side by side.

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 Block-to-Top Consistency Checking
Debugging
Context
switching

Clicking here will

analyze block
level clocks

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 Block-to-Top Consistency Checking
Summary
• Block-to-top consistency checking allows you
to quickly analyze your IP constraints and
flags potential issues
– Very accurate, behavioral checking
– Dedicated violations addressing issues specific to
this comparison

• Efficient debugging capability with dual pane

schematic and SDC viewer facilitates
debugging

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 Agenda

Galaxy Constraint Analyzer

Block-to-Top Consistency Checking

Analyze Constraints Changes

• Principle
• Use Model
• Debugging Example

Customizing Rules

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 Analyzing Constraints Changes
Need for SDC Versions Comparison

• Constraints evolve during design

 Some get added/removed
 Some get re-written more efficiently
 Some get modified automatically

• Need to verify that a given modification is:

 Either only affecting the desired objects (in the
case of constraints addition/deletion)
 Or is not changing the timing behavior of the
design (in the case of constraint optimization)

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 Analyzing Constraints Changes
1 Netlist vs. 2 SDCs

Original Modified
Design.v Constraints Constraints
(SDC or Tcl) (SDC or Tcl)

Compare 2 Constraint Sets against 1 Netlist

Violations
Report

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 Analyzing Constraints Changes
Behavior

• Galaxy Constraint Analyzer looks at the

effect each of the constraints has on the
design

• If the timing behavior of the design is

different between the two SDCs, a
violation is flagged

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 Analyzing Constraints Changes
Usage Model

• Create two scenarios

 One for the original constraints
 One for the modified constraints

• Comparison command will use the

scenario pair as the basis for comparison

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 Analyzing Constraints Changes
Example
create_clock [get_ports clk] -period 30 -waveform {0 15}
set_clock_uncertainty -setup 0.45 [get_clocks clk]
set_multicycle_path 2 -through \
[list [get_pins {u7/mult/product*}]]
set_case_analysis 1 [get_pins u5/res_reg[5]/TE]
set_multicycle_path 2 -through [list [get_pins {u5/op1[*]}]]
set_case_analysis 0 [get_ports test_se]
set_input_delay -clock clk 1.2 [all_inputs]
set_output_delay -clock clk 1.5 [all_outputs]
write_script
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create_clock -name clk -period 30 -waveform { 0 15 } [get_ports
{clk}]
set_clock_uncertainty -setup 0.45 [get_clocks {clk}]
set_multicycle_path 2 -through [get_pins {u7/mult/product[15] \
u7/mult/product[14] u7/mult/product[13] u7/mult/product[12] \
u7/mult/product[11] u7/mult/product[10] u7/mult/product[9]
u7/mult/product[8] \
u7/mult/product[7] u7/mult/product[6] u7/mult/product[5]
u7/mult/product[4] \
u7/mult/product[3] u7/mult/product[2] u7/mult/product[1]
u7/mult/product[0]}]
set_multicycle_path 2 -through [get_pins {u5/op1[15] u5/op1[14]
u5/op1[13] \
u5/op1[12] u5/op1[11] u5/op1[10] u5/op1[9] u5/op1[8] u5/op1[7]
u5/op1[6] \
u5/op1[5] u5/op1[4] u5/op1[3] u5/op1[2] u5/op1[1] u5/op1[0]}]
...
set_input_delay 1.2 -clock [get_clocks {clk}] [get_ports
{data16_a[15]}]
set_input_delay 1.2 -clock [get_clocks {clk}] [get_ports
{data16_a[14]}]
…
 Analyzing Constraints Changes
Example GUI Output Violation Details and
Debugging Hyperlinks

Dedicated
Violations

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 Analyzing Constraints Changes
Summary

• Automatic comparison of two sets of

constraints
– Verifies if two constraints sets have the same
behavior on the design
– Avoids tedious tasks of finding discrepancies
manually
– Reduces the debugging time by taking full
advantage of Galaxy Constraint Analyzer’s
debugging features

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 Agenda

Galaxy Constraint Analyzer

Block-to-Top Consistency Checking

Analyze Constraints Changes

Customizing Rules

• Why User Defined Rules?

• Rules vs. Violations
• Writing and Using User Defined Rules

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 Customizing Rules
Why User-Defined Rules?

• Built-in rules:
 Address most engineers’ needs
 Cover a wide range of checks
 But might not necessarily be a 100% match to
your design flow requirements

• You might want more rules based on:

 Company policy
 Design specific rules
 Design style

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 Customizing Rules
Introduction

 User-Defined Rules
 Tailor the set of rules exactly to your needs
• Full control on what triggers a violation
• Full control on what gets reported whenever a
violation occurs

 Very fast turnaround in rule support

• Design engineers or CAD teams can react very
quickly should a special need arise

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 Customizing Rules
Triggering a Violation
• A violation will be triggered if a certain condition is
present in the design

• Galaxy Constraint Analyzer will look for that condition

by:
 Checking for objects and their state in the design
 Checking for specific attributes applied on the design’s
objects

• Constraint Analyzer’s Tcl interface will let you query

most design object

Writing a user-defined rule = Writing Tcl code

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 Customizing Rules
What Objects Are Available?

• The objects in the design are:

– The netlist (cells, lib_cells, pin, nets…)
– The constraints (exceptions, clocks…)

• Each of those objects can also be further

refined by some attributes
– For example if a pin receives any clock, a clocks
attribute will be defined on that pin
– If a clock object is a generated clock, a special
attribute will be created

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 Customizing Rules
Use Model

• Write a Tcl procedure to check for a specific

Write a Tcl condition in the design.
checker • This procedure must contain the command
create_rule_violation which triggers a
procedure violation.

• Declare the new rule in Constraint Analyzer

Declare new rule • Associate the rule with a specific checker
procedure.

• The analyze_design command automatically

"analyze_design” runs the built-in rules *and* any user-defined
rules.

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 Customizing Rules
Writing the Tcl Checker
 Get the objects of interest: all
the hierarchical pins

proc UDEF_OutDelay_0001_Checker {} {
set hier_cells [get_cells * -filter "is_hierarchical==true“ -quiet]
set hier_pins [get_pins -of_objects $hier_cells -quiet]

foreach_in_collection pin $hier_pins {

set output_delays [get_output_delays -of_objects $pin -quiet]
if {[sizeof_collection $output_delays] > 0} {
set pin_name [get_attribute $pin full_name]
create_rule_violation -rule UDEF_OutDelay_0001 \
-parameter_values $pin_name
}
}
}

 If there is an output
delay, the design violates  For each pin, look for
our rule and triggers a an eventual output delay
violation.
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 Customizing Rules
Declaring a New Rule

create_rule -name UDEF_OutDelay_0001 -severity warning \

-message {"Output delay is specified on hierarchical\
pin '" "'."} \
-parameters {"pin"} \
-checker_proc UDEF_OutDelay_0001_Checker \
-description {“Team XYZ does not allow output delays \
to be specified on hierarchical pins”}

• create_rule declares a rule and defines

 Name of the rule (UDEF_001)
 Severity level (warning)
 Message to be displayed (-message switch)
 Description for that rule
 What Tcl checker is associated with this rule

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 Customizing Rules
Basic Example This example uses the
message only.

This area, the Info Pane, supports HTML

tags. Much more elaborate rule
messages can be created using the
combination of HTML tags and the –
details option

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 Customizing Rules
Summary
• User Defined Rules are a great way to tailor the
rule sets to your exact needs
 Enables the required quality checks for your company
and/or design

• Simple user interface allows quick and easy

development of those rules
 Every object/attribute/exception in the design can be
queried

• Seamless integration with built-in rules results in

no ramp-up time for end user

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 Summary
Advanced Features Benefits
• Faster path to tapeout with 3rd party IP integration
and constraint versions verification
 Constraints consistency can be easily verified
 Very accurate and intuitive debugging features
 Dedicated set of rules targeting specific issues to
these design stages

• Complete and extensive rule coverage through

user defined Rules
 Taylor the tool to your exact needs
 Seamless integration with standard built-in rules
 Simple Tcl procedures

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