Nikhil Balgovind Shah

Summary
• Nikhil has 20+ years of experience as a Physical design engineer
• CTS/CTMESH and clock trunk planning and analysis with clock builder tool in ICC2
• Physical-aware logic synthesis, design and verification in ICC2 for 14 nm node
• Responsible for Physical Design and Verification in Synthesis/APR ICC/ICC2 for 14 nm node
• QA Testing in smake utility of Calibre LVS, Quantus QRC and RCX Extraction for the migration
• Develop and own RTL-to-GDS implementation of multi-hierarchy and tapeouts for Digital circuits.
• Clock Skew group insertion
• Low Power UPF, SDC file creation for Synthesis and PnR
• Power gating header, sleep count, daisy chain reduce leakage
• Scripting experience in TCL
• EM/IR aging extraction with Analog AMS simulation
• Testing of Reliability Verification (RV) flows (Totem)
• RTL Digital and Analog Testcases development

SKILLS
• ICC2 Compiler, Innovus and DC Logic Synthesis and UPF with Prime power using Synopsys tools
• UPF, VCLP, Formality FEV and Cadence’s Conformal LEC
• Unix, Shell, PERL and TCL scripting, Star XT and ANSYS EMIR Redhawk tools
• PT shell, PTPX, Prime power, and Multi-voltage UPF design
• ICV, LV, ICC2 GUI and IC validator DRC tools, Calibre and Syn caliber
• Cadence Virtuoso, Spectre, Hspice, Totem RV, Voltus-FI EMIR and Cadence’s Reliability tools

EXPERIENCE
Marvell Technology Inc, Santa Clara, CA Nov 2021 – July 2022
Physical Design Engineer
• Physical Design Role of blocks in 14nm Marvell’s Dflow methodology for Government 5G Customers
• Floorplanning, flight lines, macro placement, congestion and overflow analysis using Innovus tools
• UPF based power gating, Header’s place and count, Daisy chain insertion to reduce leakage
• Dynamic power using Daisy Chaining, Sleep and Fire inputs for Always on blocks, and SAIF files
• VDD logic and VCS memory headers placement and shadow registers removal issues
• Isolation cells, Affinity buffers near the ports, clock muxes and divider port placement for timing.
• Cc-opt targets of clock skew group insertion using Innovus clock tree timing debugger tool
• Clock enable multi constraints, VT cell analysis and Crowbar Inrush current analysis
• Dflow scripts testing, PD timing spreadsheet updates from netlist to final routing stage
• Global nbias, nwelltap net connections, Multi-CUT VIA, Endfill and MimCAP rule violation fixing.

Intel Inc, San Jose, CA Dec 2020 - June 2021

CAD Engineer
• DAE role using Cadence’s Virtuoso tool for Intel’s 5G Analog products group in Oregon
• Designs of Unit Hierarchical tests of Tri-state buffers, Diff Amps, Band Gap, SERDES, ADCs and DACs.
• Testing of Reliability Verification (RV) flows using Apache Software (Totem)
• Project configuration for Clear Case in Cadence Analog products and bug tracking
• QA Testing in smake utility of Calibre LVS, Quantus QRC and RCX Extraction for the migration
• ANSYS Totem RV and Voltus-Fi EMIR benchmarks for functional accuracy and run times

Intel, San Jose, CA June 2020 - Sep 2020

Technical Architect
• Intel’s Partition Level Low Power Physical design with high-speed tools usage
• Structural Design of MGR Partitions for Xeon Scalable processors
• Syn Caliber LDRC rule checking and UPF implementation flow with physical-aware logic synthesis
• PTPX power analysis and SAIF mapping for dynamic power, VCLP design and debugging
• CTS/CTMESH and clock trunk planning and analysis with clock builder tool in ICC2
• Check FEV solution for all levels of hierarchy scalable to multiple levels of feed through insertion

IC Chip Engineering Inc, San Jose, CA Nov 2015 - Sep 2019

Physical Design Engineer
• IP Customization, RTL design and logic updates and ASIC implementation of DDR Serdes, DDR PHY and Serial
I/O interface of a DSP design of Data Interfaces
• Low power UPF flow, VCLP design and debugging and Prime Power flow for power analysis
• Physical-aware logic synthesis, design and verification in ICC2 for 14 nm node
• Worked for Clock Domain Crossing Verification teams for CDC issue closures
Intel, Hillsboro, OR June 2015 – Oct 2015
Principal Consultant
• INTEL’s Structural design of Skylake CPU partitions in Hillsboro, Oregon, FINFET -14nm
• UPF methodology, PrimePower power analysis and multi-voltage design RDT and GTI Syn/APR runs
• Top-down collateral design with Design Health checking at various stages with Prime Power
• Sync Caliber based logical DRC Lint checking and getting waivers
• Clock Attributes Automation, ICC for clock latency/skew closure and DOP placement debugging

IC Chip Engineering Inc., Hillsboro, OR Oct 2013 – May 2015

Physical Design Engineer
• Performed ASIC implementation of DDR PHY and Serial I/O interface of a DSP design
• Responsible for Physical Design and Verification in Synthesis/APR ICC/ICC2 for 14 nm node
• Worked on Floor planning and Placement and refine with multi-corner design constraints and used Prime

Cisco Corporation, San Jose, CA Jan 2011 – Sep 2013

Physical Design Engineer
• Block level design in Low power DCT and ICC compiler and 22nm planer and FINFET – 14nm
• UPF implementation flow and multi-voltage design
• PTPX power analysis and SAIF mapping for dynamic power, VCLP design and debugging
• L-MAP features for timing closure and manual refinements, RC challenges for timing

PMC Sierra Corporation, San Jose, CA Jun 2010 – Dec 2010

• DFT-RAMBIST synthesis legacy flow impl for PMC’s PCIE subsystem.
• Low power design using low power UPF Physical Design and RAMBIST synthesis flow.
• Cadence’s RTL RC compile and DFT generation of new hierarchies bolted into blocks

Avalent Technologies, San Jose, CA Aug 2008 – Apr 2009

• Design of a low cost and low power high-performance land mobile radio systems. Logic RTL DSP design in
Verilog and Physical Design for a Serial I/O Data Interface with Cartesian feed-back loop for the Mobile Radio
System with Synchronized I/Q data TX/RX.UPF implementation flow
• PTPX power analysis and SAIF mapping for dynamic power, VCLP design and debugging
• Phase Shifter with upsizing downsizing sampler generator with Interrupt request and DMA event detection at
16-bit data

Synopsys Inc. (Virage Logic Corporation), San Jose Oct 2005 - Jun 2008
• DDR2/DDR3 PHY IP customization and Verilog-RTL design updates to 90nm and 65nm nodes for Virage
libraries for NEC’s PMX chip
• Provide ASAP, IP implementation flow from RTL to GDS2 using Makefile, CVS and PERL
• Isolation of multi-Voltage power grid and UPF based power domain scripting

Broadcom Corporation, San Jose, CA Jul 2005 – Oct 2005

• Physical design of security chip, timing closures in fix time mode for early and late conditions.
• Test experience includes test-chip design, simulation, physical/functional verification, test-board assembly, chip
functional testing and characterization over voltage/temperature, silicon probing and debug, data correlation
with simulation, and bit mapping.
• Circuit design and simulation (including functional verification, model generation and verification, short loop
and critical path simulations, EM/IR analysis, and statistical analysis), and characterization methodologies.
• Experience as a liaison with product teams to coordinate deliverables.
• Debugged and solved customer issues from system level to chip level digital hardware sub-systems.
• Hardware/RTL design/review, simulation and debugging
• Board design and layout reviews (PCIe, SAS/SATA, I2C, uART interfaces)

Specular Networks, San Jose, CA Feb 2005 – Jun 2005

• Magma based synthesis and physical design for packet engine blocks including timing closure in 90nm
technology with 625 ns clock.

Intel Corp, Optical Components Division, San Jose, CA Jul 2004 - Jan 2005
• ASIC block implementations in 90 nm technology for Intel’s Optical network processor.
• Block sizes were ranged from 100K gates to 2 million gate designs
• Internal Automated flow methodologies for dc-based logic synthesis using Intel’s internal Karamba DC synthesis
Flow and Nexus APR 3.1 flow library for place and route.

Chelsio Communications / Sintegra Inc / Xellink Communications Inc / Silicon Graphics Inc / Procket Networks Inc /
Brecis Communications Inc / NeoMagic Corporation, San Jose, CA Feb 2001 - Jul 2004
• Debugged issues with timing closure and signal integrity.
• Enforced non-minimum spacing rules for clock routing and clock net extraction.
• Block level floor planning and P/R using Magma tools for an ASIC into reasonable block sizes, aspect ratio
changes to make it routable and pin optimization to remove top level congestion.
• Performed area estimation for a multi-tera bit IP/ATM ASIC core for a port controller using Magma.
• RTL design was converted to gates using fix-RTL and stabilized the scripts to run the RTL-to-Gds2 flow.
• Block level ASIC Logic Design in TERSE, DC logic Synthesis, Optimization, timing closure and design of dual
phase clocking with LSSD Scan insertion latch-based designs.
• 150 nm TSMC, 166MHz, Flip-Chip based 4 million gate BRAVO Port Processor.
• Consulting Engineer using Sapphire/FormIT logic optimization and timing closures in Prime-time SI on 180 nm
TSMC 3-4 million gate STRIPER ASIC.
• Performed all the tasks for TD placement and routing on 180 nm UMC 80MHz ASIC.

EDUCATION:
• B.S.E.E Electrical Engineering, University of Colorado 1986