What Is VHDL (IEEE Standard 1076)?

 VHDL is an acronym that stands for VHSIC Hardware Description Language.

 The acronym VHSIC in turn stands for Very-High Speed Integrated Circuit program.

 Program sponsored by US Department of Defense (DOD) with the goal of developing a

new generation of high-speed circuits.

 Increasing complexity of digital circuit design required a standardized representation

of digital circuits to that they could be shared between different designers.

 Standard representation became a digital circuit language.

 The language became the IEEE Standard 1076-1987. New features added later and
forms the IEEE Standard 1076-1993.

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VHDL vs. conventional programming languages

 a conventional programming language such as C, Pascal or Java describes a sequence

of steps on how to perform a computation.

 VHDL, on the other hand, is a language for describing a digital system.

 The description of a digital system can be used in many different ways:

 For simulating the behavior of a system without building it.

 For synthesis of an actual implementation of a system.

 So, VHDL is somewhat generic in that although we are using it for digital systems, it
does not specifically rely on any underlying implementation technology.

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Simulation and synthesis

 Simulation using a VHDL Simulator takes a VHDL description and executes the
description to mimic the behavior of the circuit in terms of events and waveforms.

 Different alternative designs can be formulated and analyzed.

 Can determine performance and correctness of a design without building it.

 Synthesis using a VHDL Compiler takes a VHDL description to generate a physical

implementation of a circuit.

 The compiler must infer hardware structures necessary to implement the

behavior described by the VHDL.

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First look at VHDL

 We can get an idea of how we can use VHDL to describe digital systems if we try to draw an analogy
between VHDL and a schematic.

 Consider the following circuit (schematic) implementing a two simple logic functions:

a
b s
c

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The VHDL
 The following is a VHDL description of the previous circuit:

-- VHDL code for First Look

a
library ieee; b s
c
use ieee.std_logic_1164.all;

entity FullAdder is
port( a,b,c : in std_logic; z
s,z : out std_logic);
end FullAdder;

architecture prototype of FullAdder is

begin
s <= a xor b xor c; -- equation for s
z <= (a and b) or (a and c) or (b and c); -- equation for z
end prototype;

 We can simulate the design using a VHDL Simulator to test correct functionality or we can
synthesis the design to get a circuit (in some technology).

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Simulation of example

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 Delays…
 Just a reality check… Real circuits with gates have delays. Using VHDL, you an also
specify delays.

-- VHDL code for First Look

a
library ieee; b 2 s
use ieee.std_logic_1164.all; c
2
entity FullAdder is
port( a,b,c : in std_logic;
2 2 z
s,z : out std_logic);
end FullAdder;
2
architecture prototype of FullAdder is
begin
s <= a xor b xor c after 2 ns; -- equation for s
z <= (a and b) or (a and c) or (b and c) after 4 ns; -- equation for z
end prototype;

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Simulation of example with delays

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Structure of a VHDL description
 We can look at the VHDL code to understand the syntax.

-- VHDL code for First Look

library ieee;
use ieee.std_logic_1164.all;

entity FullAdder is
port( a,b,c : in std_logic;
s,z : out std_logic);
end FullAdder;

architecture prototype of FullAdder is

begin
s <= a xor b xor c; -- equation for s
z <= (a and b) or (a and c) or (b and c); -- equation for z
end prototype;

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Comments
 We can have comments in a VHDL Description just like in a computer program.

 The can be on a line by themselves, or after other VHDL syntax.

 Comments are preceded by a double dash.

 Our VHDL Description has several comments.

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Design entities and design architectures
 The VHDL description of a circuit is called a design entity and consists of two main
parts:

 Entity declaration.

 Architecture definition.

 The entity declaration describes the interface to the rest of the world; i.e., the inputs
and outputs of the circuit.

 The architecture definition describes one particular implementation of the circuit.

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Data objects and signals
 VHDL stores information via data objects.

 We can have three types of data objects:

 Signals.
 Constants.
 Variables.

 We will mostly be concerned with signals.

 We can think of signals as the wires in our circuit.

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Naming conventions
 Signals have names and we must adhere to the VHDL naming convention.

 Signal names can contain any alpha-numeric characters and the underscore.

 Restrictions on signal names:

 Must begin with a letter.

 Can’t have two successive underscores.
 Can’t end with an underscore.
 Can’t be a VHDL reserved word.
 CASE INSENSITIVE.

 In our example, we have 5 signals: a, b, c, s and z.

 Data objects have types (we will consider this later, but in our example all signals are type
std_logic).

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Signal declarations
 Like variables in a computer program, signals need to be declared.

 Signals can be declared inside three places in a VHDL Description:

 Port of an Entity Declarations.

 Declarations section of an Architecture Description.

 Declarations section of a Package.

 We will consider declarations in these different places later.

 In our example, our 5 signals are declared inside of the Port of the Entity
Declaration.

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Entity declaration syntax
 Entity Declarations have a specific syntax:

ENTITY entity_name IS
PORT(
SIGNAL signal_name : mode type ;
SIGNAL signal_name : mode type ;
…
SIGNAL signal_name : mode type ) ;
END entity_name;

 Entity Declarations have a name and a port. The port basically is where the inputs
and outputs of the circuit are listed.

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Architecture definition syntax
 Architecture Definitions have a specific syntax:

ARCHITECTURE architecture_name OF entity_name IS

-- declarative section
[SIGNAL declarations]
[CONSTANT declarations]
[TYPE declarations]
[COMPONENT declarations]
[ATTRIBUTE declarations]
BEGIN
-- implementation
[COMPONENT instantiation statements]
[CONCURRENT ASSIGNMENT statements]
[PROCESS statements]
[GENERATE statements]
END architecture_name ;

 We will worry about the different sections and possibilities as we need them.

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Operators
 We can have operators in VHDL Descriptions:

 Boolean Operators
 AND, OR, NOT, XOR, NAND, NOR, etc...

 Relational Operators
 = (equality), /= (not equality), < (less than), > (greater than), etc…

 Arithmetic Operators
 +, -, &, etc.

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Concurrent signal assignment syntax
 We need to be able to assign values to signals.

 One way of accomplishing this is via a concurrent signal assignment “<=“.

 Concurrent signal assignments have the syntax:

Signal_name <= expression ;

 In our example, we have 2 concurrent signal assignments in order to assign the

outputs to s and z.

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Concept of concurrency (1)
 VHDL is intended to describe the behavior of digital hardware systems.

 In digital hardware systems, things operate in parallel.

 So, unlike a conventional programming language like C, Pascal or Java, we need to

understand that in VHDL the order of assignments is not important; i.e., we program
with the notion of concurrency.

 E.g., all concurrent signal assignments operate in parallel, and all left-hand sides (new
values at time t+ t) get undated from the right-hand sides using the values at time t.

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Concept of concurrency (2)
 So, in our example, the following VHDL descriptions are equivalent (order of s and z
reversed).

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

entity FullAdder is entity FullAdder is

port( a,b,c : in std_logic; port( a,b,c : in std_logic;
s,z : out std_logic); s,z : out std_logic);
end FullAdder; end FullAdder;

architecture prototype of FullAdder is architecture prototype of FullAdder is

begin Begin
s <= a xor b xor c; z <= (a and b) or (a and c) or (b and c);
z <= (a and b) or (a and c) or (b and c); s <= a xor b xor c;
end prototype; end prototype;

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Concept of concurrency (3)
 The following ordering of signals is also equivalent (notice that in this example, one
signal on the left-hand side depends on the other…)

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

entity Concurrent is entity Concurrent is

port( a,b,c : in std_logic; port( a,b,c : in std_logic;
d,e : inout std_logic); d,e : inout std_logic);
end Concurrent; end Concurrent;

architecture prototype of Concurrent is architecture prototype of Concurrent is

begin Begin
e <= c or d after 2 ns; d <= a and b after 2 ns;
d <= a and b after 2 ns; e <= c or d after 2 ns;
end prototype; end prototype;

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Signal modes (1)
 When declared inside of the port of an entity declaration, we must give the signal a
mode.

 The mode can be 1 of 4 values and basically tells us the direction of the signal.

 IN --
 Data flows along the signal into the circuit.
 OUT --
 Data flows along the signal out of the circuit.
 BUFFER --
 Data flows along the signal out of the circuit, but is used internally inside of the
circuit.
 INOUT --
 Data flows along the signal both into and out of the circuit.

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Signal modes (2)

IN OUT

IN BUFFER

IN INOUT
IN

OUT

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Signal types
 Signals must have a type.

 Consider real wires in a digital circuit. The logical values 0 and 1 are represented by
voltages, and are not sufficient:
 What if a signal is not driven to a certain value because a wire is disconnected or
temporarily disconnected?
 What if accidentally a signal is concurrently driven to both 0 and 1… What is its
correct value?
 What if the initial value of a signal is not defined?
 Since signals are implemented physically with wires, how can we represent the
strength of a signal?

 In the early days of VHDL, different tool vendors had their own ways to represent the
above situations.
 This (again) made it hard to share VHDL descriptions.

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IEEE Standard 1164 (1)
 A numeric standard that attempts to establish a common ground for signal values to
enable sharing of VHDL descriptions.

 Approved a 9-valued system:

 Note: from the perspective of synthesis, the 9-valued system is slightly different
than for simulation. E.g., when circuits are synthesized unknown or un-initialized
values do not have any meaning – no physical representation for such situations.

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IEEE Standard 1164 (2)
 A signal type std_ulogic following this standard is defined as follows:

type std_ulogic is (
‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘1’, -- Forcing 1
‘0’, -- Forcing 0
‘Z’, -- High impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- Don’t care
);

 This type is defined in the IEEE library in the 1164 package (more in a minute).

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IEEE Standard 1164 (3)
 Because we can have multiple sources driving a wire, we need a resolved type.
 i.e., when multiple sources drive a wire (possibly with different values), we
need to decide on one value for the driven wire.

 The IEEE 1164 Standard also defines the signal type std_logic. It has the same values
as std_ulogic, determined according to the following table (if multiple drivers).

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IEEE Standard 1164 (4)
 We will see that sometimes we can have vectors of signals. We have two more types
defined, namely std_ulogic_vector and std_logic_vector.

 These are defined as follows (for example):

signal signal_name : std_logic_vector(7 downto 0);

 Note: if std_logic_vector is a type declared in the port of an entity, then we also

need a signal mode.

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What is a Library?
 A library is a repository for frequently used design entities (consider a library to be
much like an include file in a C program) that we wish to share.

 The VHDL library IEEE; in our VHDL Descriptions simply identifies a library that we
wish to access.

 The library name is a logical name and in practice usually just maps to a directory on
the computer in which various design units have been precompiled and stored.

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What is a Package?
 A package is a design unit that contains different types of useful stuff, like definitions
of signal types, functions and procedures, etc… usable in our VHDL Descriptions.

 The VHDL use ieee.std_logic_1164.all; means that we want to use the std_logic_1164
package which is stored inside the IEEE library.

 The “.all” simply means that we want access to everything stored inside of the
package.

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In Our VHDL Descriptions…
 We need to identify this library (IEEE) and this package (std_logic_1164) in order to
use signal types std_logic and std_logic_vector in our VHDL Descriptions.

 So, we always place the following VHDL prior to every entity declaration.

-- following lines before every VHDL entity declaration.

Library ieee;
Use ieee.std_logic_1164.all;

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Example revisited
 We should now be able to re-examine our original VHDL Description and identify
the meaning of every line of VHDL.

-- VHDL code for First Look

a
library ieee; b s
c
use ieee.std_logic_1164.all;

entity FullAdder is
port( a,b,c : in std_logic; z
s,z : out std_logic);
end FullAdder;

architecture prototype of FullAdder is

begin
s <= a xor b xor c; -- equation for s
z <= (a and b) or (a and c) or (b and c); -- equation for z
end prototype;

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Another simple example (1)
 Implement the sum-of-products expression f = (0,1,3,4,5) via a VHDL Description.

 Ignoring the library and use statements (just put them at the top of the VHDL
description), we should be able to layout the entire VHDL Description.

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Another simple example (2)

-- VHDL code for Second Simple Example

library ieee;
use ieee.std_logic_1164.all;

entity SomeFunction is
port( a,b,c : in std_logic;
f : out std_logic);
end SomeFunction;

architecture prototype of SomeFunction is

begin
f <= ((not a) and (not b) and (not c)) -- m0
or ((not a) and (not b) and c) -- m1
or ((not a) and b and c) -- m3
or (a and (not b) and (not c)) -- m4
or (a and (not b) and c) ; -- m5
end prototype;

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Another simple example (3)

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