Digital Design Flow

Digital Design Flow begins with specification of the design at various

levels of abstraction.

Design entry phase: Specification of design as a mixture of behavioral

Verilog code, instantiation of Verilog modules, and bus and wire
assignments

Verilog Digital System Design

Z. Navabi, 2006 1
 Digital Design Flow
Design Entry in Verilog
module design (. . .); Comp1 U1 (. . .); always (posedge clk)
assign . . . Comp2 U2 (. . .); begin . . . end
always . . . ...
Testbench in Verilog compi (. . .) if () bus = w;
Compn Un (. . .);
module testbench (); endmodule else . . .
generate data;
process data;
endmodule

Behavioral Simulation Assertion Verification Formal Verification

Violation Report; Pass / Fail Report

Time of Violation; Property Coverage
Monitor Coverage Counter Examples

Compilation and Synthesis

Analysis Synthesis Routing and placement

C++ Classes, Y=a&d&w

Language Representation w=a&b|c

Timing Analysis

2 ns 1.6 ns

Post-synthesis Simulation

Device Programming ASIC Netlist Custom IC Layout

EDIF

FPLD Design Flow 1010... or other netlists

Verilog Digital System Design

Z. Navabi, 2006 2
 Digital Design Flow
Design Entry
Phase

Design Entry in Verilog

module design (. . .); Comp1 U1 (. . .); always (posedge clk)
assign . . . Comp2 U2 (. . .); begin . . . end
always . . . ...
Testbench in Verilog compi (. . .) if () bus = w;
Compn Un (. . .);
module testbench (); endmodule else . . .
generate data;
process data;
endmodule

Behavioral Simulation Assertion Verification Formal Verification

Violation Report; Pass / Fail Report

Time of Violation; Property Coverage
Monitor Coverage Counter Examples

FPLD Design Flow

Verilog Digital System Design

Z. Navabi, 2006 3
 Digital Design Flow

Presynthesis verification: Generating testbenches for verification of the

design and later for verifying the synthesis output

Verilog Digital System Design

Z. Navabi, 2006 4
 Digital Design Flow
Behavioral Simulation Assertion Verification Formal Verification

Violation Report; Pass / Fail Report

Time of Violation; Property Coverage
Monitor Coverage Counter Examples

Compilation and Synthesis

Analysis Synthesis Routing and placement

C++ Classes, Y=a&d&w

Language Representation w=a&b|c

Timing Analysis
Presynthesis
Verification
FPLD Design Flow 2 ns 1.6 ns
(Continued)
Verilog Digital System Design
Z. Navabi, 2006 5
 Digital Design Flow

Synthesis process: Translating the design into actual hardware of a

target device (FPLD, ASIC or custom IC)

Verilog Digital System Design

Z. Navabi, 2006 6
 Digital Design Flow
Behavioral Simulation Assertion Verification Formal Verification

Violation Report; Pass / Fail Report

Time of Violation; Property Coverage
Monitor Coverage Counter Examples

Compilation and Synthesis

Analysis Synthesis Routing and placement

C++ Classes, Y=a&d&w

Language Representation w=a&b|c

Timing Analysis
Synthesis Process
FPLD Design Flow 2 ns 1.6 ns
(Continued)
Verilog Digital System Design
Z. Navabi, 2006 7
 Digital Design Flow

Postsynthesis simulation: Testing the behavioral model of the design

and its hardware model by using presynthesis test data

Verilog Digital System Design

Z. Navabi, 2006 8
 Digital Design Flow
Testbench in Verilog Timing Analysis
module testbench ();
generate data;
process data;
endmodule 2 ns 1.6 ns

Post-synthesis Simulation
Postsynthesis
Verification

Device Programming ASIC Netlist Custom IC Layout

EDIF
1010... or other netlists

FPLD Design Flow (Continued)

Verilog Digital System Design
Z. Navabi, 2006 9
 Digital Design Flow

Digital Design Flow ends with generating netlist for an application

specific integrated circuits (ASIC), layout for a custom IC, or a program
for a programmable logic devices (PLD)

Verilog Digital System Design

Z. Navabi, 2006 10
 Digital Design Flow
Testbench in Verilog Timing Analysis
module testbench ();
generate data;
process data;
endmodule 2 ns 1.6 ns

Post-synthesis Simulation

Device Programming ASIC Netlist Custom IC Layout

EDIF
1010... or other netlists

FPLD Design Flow (Continued)

Verilog Digital System Design
Z. Navabi, 2006 11
 Digital Design Flow
Digital Design
Flow

Design Entry Testbench in Verilog

Compilation
Design Validation
and Synthesis
Postsynthesis Timing
Simulation Analysis
Hardware
Generation
Verilog Digital System Design
Navabi, 2006 12
 Verilog HDL

A language that can be understood by:

System Designers

RT Level Designers,

Test Engineers

Simulators

Synthesis Tools

Machines

Has become an IEEE standard

Verilog Digital System Design

Z. Navabi, 2006 13
 The Verilog Language
The Verilog HDL satisfies all requirements for design and synthesis of
digital systems:

Supports hierarchical description of hardware from system to gate

or even switch level.
Has strong support at all levels for timing specification and
violation detection.
A hardware component is described by the module_declaration
language construct in it.

Verilog Digital System Design

Z. Navabi, 2006 14
 The Verilog Language
The Verilog HDL satisfies all requirements for design and synthesis of
digital systems (Continued):

Description of a module specifies a components input and output

list as well as internal component busses and registers within a
module, concurrent assignments, component instantiations, and
procedural blocks can be used to describe a hardware component.
Several modules can hierarchically be instantiated to form other
hardware structure.
Simulation environments provide graphical front-end programs and
waveform editing and display tools.
Synthesis tools are based on a subset of Verilog.

Verilog Digital System Design

Z. Navabi, 2006 15
 Elements of Verilog

We discuss basic constructs of Verilog language for describing a

hardware module.

Verilog Digital System Design

Z. Navabi, 2006 16
 Elements of Verilog
Hardware
Modules

Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 17
 Hardware Modules
Hardware
Modules
Modules

Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 18
 Hardware Modules
module :
The Main
Keyword
Component
module of Verilog

module module-name
Variables, wires, and
List of ports; module parameters
Declarations are declared.
...
Functional specification of module
...
Keyword
endmodule endmodule

Module Specifications

Verilog Digital System Design

Z. Navabi, 2006 19
 Hardware Modules

There is more than one way to describe a Module in Verilog.

May correspond to descriptions at various levels of abstraction or to
various levels of detail of the functionality of a module.
We show a small example and several alternative ways to describe it in
Verilog.

Verilog Digital System Design

Z. Navabi, 2006 20
Primitive Instantiations
Hardware
Modules

Primitive
Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 21
 Primitive Instantiations
Logic Gates
called
Primitives
a a_sel

s_bar w
s
b b_sel
A Multiplexer Using Basic Logic Gates

Verilog Digital System Design

Z. Navabi, 2006 22
 Primitive Instantiations

module MultiplexerA (input a, b, s, output w);

wire a_sel, b_sel, s_bar;
not U1 (s_bar, s);
and U2 (a_sel, a, s_bar); Instantiation
of Primitives
and U3 (b_sel, b, s);
or U4 (w, a_sel, b_sel);
endmodule

Primitive Instantiations

Verilog Digital System Design

Z. Navabi, 2006 23
 Assign Statements
Hardware
Modules

Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 24
 Assign Statements
Continuously
drives w with the
right hand side
expression

module MultiplexerB (input a, b, s, output w);

assign w = (a & ~s) | (b & s);
endmodule
Using Boolean
Assign Statement and Boolean expressions to
describe the logic

Verilog Digital System Design

Z. Navabi, 2006 25
Condition Expression
Hardware
Modules

Primitive Assign
Instantiations Statements

Condition
Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 26
 Condition Expression
Can be used when
the operation of a
unit is too complex
to be described by
Boolean expressions

module MultiplexerC (input a, b, s, output w);

assign w = s ? b : a;
endmodule

Assign Statement and Condition Operator

Very Effective in
describing complex
Useful in describing a functionalities
behavior in a
very compact way

Verilog Digital System Design

Z. Navabi, 2006 27
 Procedural Blocks
Hardware
Modules

Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 28
 Procedural Blocks
always
statement Sensitivity list

module MultiplexerD (input a, b, s, output w);

reg w;
always @(a, b, s) begin
if (s) w = b;
else w = a;
end if-else Can be used when the
endmodule statement operation of a unit is
too complex to be
Procedural Statement described by Boolean or
conditional expressions

Verilog Digital System Design

Z. Navabi, 2006 29
Module Instantiations
Hardware
Modules

Primitive Assign
Instantiations Statements

Condition Procedural
Expression Blocks

Module
Module
Instantiations
Verilog Digital System Design
Z. Navabi, 2006 30
 Module Instantiations

module ANDOR (input i1, i2, i3, i4, output y);

ANDOR
assign y = (i1 & i2) | (i3 & i4); module is
endmodule defined
//
module MultiplexerE (input a, b, s, output w);
wire s_bar;
not U1 (s_bar, s);
ANDOR U2 (a, s_bar, s, b, w);
ANDOR
endmodule module is
Module Instantiation instantiated

Verilog Digital System Design

Z. Navabi, 2006 31
 Module Instantiations

a
ANDOR
i1
s i2 y w
i3
b i4

Multiplexer Using ANDOR

Verilog Digital System Design

Z. Navabi, 2006 32
Component Description
in Verilog
Component
Description

Data
Controllers
Components

Verilog Digital System Design

Z. Navabi, 2006 33
Data Components

Component
Description

Data
Data
Controllers
Components
Components

Verilog Digital System Design

Z. Navabi, 2006 34
 Data Components
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 35
 Multiplexer
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 36
 Multiplexer
Defines a Time Unit of 1 ns
and Time Precision of 100 ps.

`timescale 1ns/100ps

module Mux8 (input sel, input [7:0] data1, data0,

output [7:0] bus1);
assign #6 bus1 = sel ? data1 : data0;
endmodule
A 6-ns Delay
Octal 2-to-1 MUX Selects its 8-bit
is specified for all data0 or data1 input
values assigned to depending on its
bus1 sel input.

Verilog Digital System Design

Z. Navabi, 2006 37
 Flip-Flop
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 38
 The Body of
always statement is
executed at the Flip-Flop Flip-Flop
negative edge of Synchronous
the clk signal reset input triggers on the
falling edge of
`timescale 1ns/100ps clk Input

module Flop (reset, din, clk, qout);

input reset, din, clk; A Signal declared as a
output qout; reg to be capable of
reg qout; holding its values
always @(negedge clk) begin between clock edges
if (reset) qout <= #8 1'b0;
else qout <= #8 din;
end
endmodule A Non-blocking
An 8-ns Assignment
Flip-Flop Description Delay

Verilog Digital System Design

Z. Navabi, 2006 39
 Counter
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 40
A 4-bit modulo-16
Counter
Counter 4-bit
Register

`timescale 1ns/100ps
module Counter4 (input reset, clk,
output [3:0] count);
reg [3:0] count; Constant
always @(negedge clk) begin Definition
if (reset) count <= #3 4'b00_00;
else count <= #5 count + 1;
end When count
endmodule reaches 1111,
the next count
Counter Verilog Code taken is 10000

Verilog Digital System Design

Z. Navabi, 2006 41
 Full-Adder
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 42
 Full-Adder
All Changes
A combinational
Occur after 5 ns
circuit

`timescale 1ns/100ps

module fulladder (input a, b, cin, output sum, cout);

assign #5 sum = a ^ b ^ cin;
assign #3 cout = (a & b)|(a & cin)|(b & cin);
endmodule

Full-Adder Verilog Code

All Changes
One delay for Occur after 3 ns
every output:
tPLH and tPHL

Verilog Digital System Design

Z. Navabi, 2006 43
 Shift-Register
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 44
 An 8-bit
2 Mode inputs Shift-Register Universal
Shift Register
m[1:0] form a
`timescale
2-bit number 1ns/100ps

module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
Case Statement
input [1:0] m, output
With 4 reg [7:0] ParOut);
case-alternatives
and default Value
always @(negedge clk) begin
case (m)
m=0 : Does Nothing
0: ParOut <= ParOut;
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr}; m=1,2: Shifts Right
3: ParOut <= ParIn; and Left
default: ParOut <= 8'bX;
endcase m=3 : Loads its Parallel
end input into the register
endmodule

Verilog Digital System Design

Z. Navabi, 2006 45
 Shift-Register (Continued)
`timescale 1ns/100ps

module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
input [1:0] m, output reg [7:0] ParOut);
Shift Right:
The SL input is
always @(negedge clk) begin
concatenated to
case (m) the left of
0: ParOut <= ParOut; ParOut
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr};
3: ParOut <= ParIn;
default: ParOut <= 8'bX; Shifting the
endcase ParOut to the left
end
endmodule

Verilog Digital System Design

Z. Navabi, 2006 46
 ALU
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 47
 ALU
`timescale 1ns/100ps

module ALU8 (input [7:0] left, right, 2-bit mode Input

input [1:0] mode, to select one of its
output reg [7:0] ALUout); 4 functions
always @(left, right, mode) begin
case (mode)
0: ALUout = left + right;
1: ALUout = left - right; Add
2: ALUout = left & right; Subtract
3: ALUout = left | right; AND
default: ALUout = 8'bX; OR
endcase
end
endmodule

An 8-bit ALU
Verilog Digital System Design
Z. Navabi, 2006 48
 ALU (Continued) The Declaration of
ALUout both as
`timescale 1ns/100ps output and reg:
Because of
module ALU8 (input [7:0] left, right, assigning it within
input [1:0] mode, a Procedural Block
output reg [7:0] ALUout);
always @(left, right, mode) begin
case (mode) Blocking
0: ALUout = left + right; Assignments
1: ALUout = left - right;
2: ALUout = left & right;
3: ALUout = left | right;
default: ALUout = 8'bX; default alternative
endcase puts all Xs on ALUOut
end if mode contains
endmodule anything but 1s and 0s

An 8-bit ALU
Verilog Digital System Design
Z. Navabi, 2006 49
 Interconnections
Data
Components

Multiplexer Flip-Flop

Counter Full-Adder

Shift-Register ALU

Interconnections
Verilog Digital System Design
Z. Navabi, 2006 50
 Interconnections
Inbus Aside Bside

8 8

select_source

Mux8 and ALU 8 8

examples forming a ABinput
Partial Hardware
Function

8
Outbus
Partial Hardware Using MUX8 and ALU

Verilog Digital System Design

Z. Navabi, 2006 51
 Interconnections
A Set of parenthesis
Instantiation of enclose port
ALU8 and MUX8 connections to the
instantiated modules

ALU8 U1 ( .left(Inbus), .right(ABinput),

.mode(function), .ALUout(Outbus) );
Mux8 U2 ( .sel(select_source), .data1(Aside),
.data0(Bside), .bus1 (ABinput));

u1 Verilog
and u2 : Code of The Partial Hardware Example
Instance Names

Verilog Digital System Design

Z. Navabi, 2006 52
 Interconnections
The actual ports
of the instantiated
An Alternative format components
of port connection are excluded

ALU8 U1 ( Inbus, ABinput, function, Outbus );

Mux8 U2 ( select_source, Aside, Bside, ABinput );

Ordered Port Connection

The list of local signals
in the same order as
their connecting ports

Verilog Digital System Design

Z. Navabi, 2006 53
 Controllers

Component
Description

Data
Controllers
Controllers
Components

Verilog Digital System Design

Z. Navabi, 2006 54
 Controllers

Decisions
Based on :Inputs ,
Outputs ,State

Issue Control Signal

Set Next State

Go to Next State
Controller Outline

Verilog Digital System Design

Z. Navabi, 2006 55
 Controllers

Controller:
Is wired into data part to control its flow of data.

The inputs to it controller determine its next states and outputs.

Monitors its inputs and makes decisions as to when and what output
signals to assert.
Keeps the history of circuit data by switching to appropriate states.

Two examples to illustrate the features of Verilog for describing state

machines:
Synchronizer

Sequence Detector

Verilog Digital System Design

Z. Navabi, 2006 56
 Controllers

Controllers

Sequence
Synchronizer
Detector

Verilog Digital System Design

Z. Navabi, 2006 57
 Synchronizer

Controllers

Sequence
Synchronizer
Synthesizer
Detector

Verilog Digital System Design

Z. Navabi, 2006 58
 Synchronizer

Clk

adata

synched

Synchronizing adata

Verilog Digital System Design

Z. Navabi, 2006 59
 Synchronizer

`timescale 1ns/100ps

module Synchronizer (input clk, adata,

output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0; If a 1 is Detected on
else synched <= 1; adata on the rising
endmodule edge of clock,
synched becomes 1
A Simple Synchronization Circuit and remains 1
for at least one
clock period

Verilog Digital System Design

Z. Navabi, 2006 60
Sequence Detector

Controllers

Sequence
Sequence
Synthesizer
Detector
Detector

Verilog Digital System Design

Z. Navabi, 2006 61
 Sequence Detector
When the sequence
Searches on is detected, the w
its a input Output becomes 1
for the and stays 1 for a
110 Sequence complete clock cycle
If 110 is detected
a on a, then w gets w
1, else w gets 0.

clk
State Machine Description

Verilog Digital System Design

Z. Navabi, 2006 62
 Sequence Detector
A Moore Machine
Sequence Detector
States are named: The State in which
s0 , s1 , s2 , s3 the 110 sequence is
detected.
0 1
reset
1 1 0
S0 S1 S2 S3
0 0 0 0 1
1
Initia
l 0
State
It Takes at least
3 clock periods to
get to the s3 state
Sequence Detector State Machine

Verilog Digital System Design

Z. Navabi, 2006 63
 Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;

always @(posedge clk) begin

if (reset) current = s0;
else
case (current)
s0: if (a) current <= s1; else current <= s0;
s1: if (a) current <= s2; else current <= s0;
s2: if (a) current <= s2; else current <= s3;
s3: if (a) current <= s1; else current <= s0;
endcase
end

assign w = (current == s3) ? 1 : 0;

endmodule

Verilog Code for 110 Detector

Verilog Digital System Design
Z. Navabi, 2006 64
 Sequence Detector Description
Behavioral
of the
State Machine
module Detector110 (input a, clk, reset, output w);

parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10,

s3=2'b11;

reg [1:0] current; A 2-bit Register Parameter declaration

defines constants
always @(posedge clk) begin s0, s1, s2, s3
if (reset) current = s0;
else
...........................
...........................

Verilog Code for 110 Detector

Verilog Digital System Design

Z. Navabi, 2006 65
 Sequence Detector
...........................
...........................
always @(posedge clk) begin if-else statement
if (reset) current = s0; checks for reset
else
At the case (current)
Absence of s0: if (a) current <= s1; else current <= s0;
a 1 on reset s1: if (a) current <= s2; else current <= s0;
s2: if (a) current <= s2; else current <= s3;
s3: if (a) current <= s1; else current <= s0;
endcase
end The 4 Case-alternatives
each correspond to a
Verilog Code for 110 Detector state of state machine

Verilog Digital System Design

Z. Navabi, 2006 66
 Sequence Detector

s1 s1:
0
a=1 if (a)

s2 current <= s2;

0
a=0 else

s0 current <= s0;

0

State Transitions on Corresponding Verilog Code

Verilog Digital System Design

Z. Navabi, 2006 67
 Sequence Detector
Outside of the
always Block:
A combinational
end circuit
............................
............................
assign w = (current == s3) ? 1 : 0;
Assigns a 1 to w
endmodule output when
Machine Reaches to
Verilog Code for 110 Detector s3 State

Verilog Digital System Design

Z. Navabi, 2006 68