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• Assumes sender is ready to send data and receiver ready to receive data on each
cycle (How about for cases where the assumption does not hold?)
• If the system uses a synchronizer output and the output is still in metastable state,
then it will lead to synchronizer failure.
• If the clock period is greater than the metastability resolution time plus FF2 setup
time, FF2 gets synchronized version of ASYNCIN.
• Producer can perform many writes without consumer performing any reads (or vice
versa). However, because of finite buffer size, FIFO memories, on average, need
equal number of reads and writes.
• Typical uses:
• Interfacing I/O devices, such as network interface: Data bursts from network, then
processor bursts to memory buffer (operations not synchronized)
• Audio output: The processor produces output samples in bursts. Audio DAC clocks it out
at constant sample rate.
endmodule
CoE 111: ADVANCED DIGITAL DESIGN 10
Memory Inference
// implementation of 64x1 RAM with synchronous read
module ram64x1(clk, we, d, addr, q);
input clk, we, d;
input [5:0] addr;
output reg q;
endmodule
CoE 111: ADVANCED DIGITAL DESIGN 11
Memory Inference
// implementation of a dual-read port 64x16 RAM
reg [15:0] ram [63:0];
always@(posedge clk)
if (we)
ram[wr_addr] <= din;
initial begin
$readmemh(“data.txt”, ram);
end
CoE 111: ADVANCED DIGITAL DESIGN 13
FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
input clk, nrst, WE, RE;
input [7:0] DIN;
output [7:0] DOUT;
output full, empty;
reg [7:0] memory [0:3];
reg [1:0] head, tail;
...
endmodule
always@(posedge clk)
if (WE)
memory[tail] <= DIN;
...
endmodule
CoE 111: ADVANCED DIGITAL DESIGN 15
FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
...
reg [7:0] DOUT;
always@(posedge clk)
if (!nrst)
DOUT <= 0;
else
if (RE)
DOUT <= memory[head];
always@(posedge clk)
if (!nrst)
head <= 0;
else
if (RE)
head <= head + 1;
...
endmodule
CoE 111: ADVANCED DIGITAL DESIGN 16
FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
...
reg [2:0] count;
always@(posedge clk)
if (!nrst)
count <= 0;
else
case ({WE, RE})
2'b10: count <= count + 1;
2'b01: count <= count - 1;
endcase
always@(posedge clk)
if (!nrst)
count <= 0;
else
if ((count == 0) && (en))
count <= count + 1;
else
if (count < 4’d13)
count <= count + 1;
// 1-bit adder
wire sum_1b, cout;
reg cin, init_cin;
assign {cout, sum_1b} = {1’b0, opA[0]} + {1’b0, opB[0]} + cin;
always@(posedge clk)
if (!nrst) cin <= 0;
else
if (init_cin) cin <= 0;
else cin <= cout;
// controller: done
always@(*)
if (state == 2’d3)
done <= 1’b1;
else
done <= 0;
// clock generator
always
#5 clk = ~clk;
// instantiation
serial_adder UUT(clk, nrst, en, a, b, sum);
initial begin
no_tests = 10;
nrst = 0;
en = 0;
clk = 0;
#8
nrst = 1’b1;
...
end
CoE 111: ADVANCED DIGITAL DESIGN 34
Example
Serial Adder Test
initial begin
...
for (i=0; i<no_tests; i=i+1) begin
#10
current_test = test[i];
a = current_test[15:8];
b = current_test[7:0];
en = 1’b1;
#10
en = 0;
while(!done) begin #10; end
if (sum == (a + b))
$display(“%d+%d=%d correct”, a, b, sum);
else
$display(“%d+%d=%d wrong”, a, b, sum);
end
end
CoE 111: ADVANCED DIGITAL DESIGN 35