Department of Electronics & Communication Engineering

Major Project
on
ANALOG DESIGN OF ASYNCHRONOUS SUCCESSIVE
APPROXIMATION BASED ANALOG TO DIGITAL CONVERTER
Meenakshi Kangoori - 2VD18EC038
Prerna Jainapur - 2VD18EC058
Priyanka Kumbar - 2VD18EC059
Sneha Hiregoudar - 2VD18EC089

Under the Guidance of

Dr. Vikas Balikai
Asst. Professor
Dept of ECE, KLS VDIT, Haliyal
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

Outline
1.PROBLEM STATEMENT
2.INTRODUCTION
3.OBJECTIVE
4.LITERATURE SURVEY
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

1. PROBLEM STATEMENT
Analog Design of Asynchronous Successive
Approximation based Analog to Digital
Converter
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

2.INTRODUCTION

 Analog-to-Digital Converters (ADC) are required for interfacing analog signals to digital
circuits. ADC provides connection between hardware systems and digital signal processing
systems.
 SAR ADC is known for its simple structure, thus consuming less power and saving more
size.
 Among the various architectures of ADCs, the successive approximation register (SAR)
ADC has attracted more attention in recent years due to its excellent power efficiency and
suitability for medium-to-high-speed applications.
 In the past few years, demand of SAR ADC is increased because more and more
applications are built with very stringent requirements on power consumption. For
electronic systems, such as wireless systems or portable devices, the power consumption is
one of the most critical factors.
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

3.OBJECTIVES
 To design an 8-bit asynchronous successive approximation register (SAR)
analog-to-digital converter (ADC) using 90nm CMOS technology

.
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

4.LITERATURE SURVEY

Reference 1
Author name: Yongfu Li and Yong Lian
Topic: A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing
Published On: February 2019
Description: In this paper, a 12-bit 1-kS/s successive approximation register analog-todigital converter
(ADC) is presented for biomedical signal processing system. The proposed ADC is fabricated in 130-
nm CMOS process with a core area of 0.16

Reference 2
Author name: Raheleh Hedayati
Topic: A Study of Successive Approximation Registers and Implementation of an UltraLow Power
10-bit SAR ADC in 65nm CMOS Technology
Published On: September 2011
Description: In this paper the Successive Approximation Register (SAR) Analog-to-Digital Converter in
medical application such as pacemaker. This thesis work initially investigates and compares different
structures of SAR control logics including the conventional structures and the delay line based controller
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

Reference 3
Author name: Jai-Ming Lin and Ya-Ting Shyu
Topic: A Systematic Design Methodology of Asynchronous SAR ADCs
Published On: May 2016
Description: This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on
design considerations. A sizing tool based on the proposed design procedure is also implemented, the
sizing results of which are highly competitive in comparison with other state-of-the-art manual works.

Reference 4
Author name: Jeffrey Fredenburg and Michael P. Flynn
Topic: ADC Trends and Impact on SAR ADC Architecture and Analysis
Published On: 2015
Description: This paper reviews the fundamental limits of the energy efficiency of the SAR architecture,
considering the energy consumption of the capacitor array and of the comparator. ADCs. ADC yield as a
function of capacitor matching is also considered
 Analog Design of Asynchronous Successive Approximation Analog to Digital converter

Reference 5
Author name: Deeksha Verma , Khuram Shehzad and Danial Khan
Topic: A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
Published On: July 2020
Description: To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a
common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The
proposed switching technique consumes only 63.75 CVREF 2 switching energy, which is far less as
compared to the conventional switching technique without dividing or adding additional switches.
Analog Design of Asynchronous Successive Approximation Analog to Digital converter