Module5-Design of Sequential

Logic Circuits
Module 5
 Module 5-Design of Sequential
Logic Circuits
• Latches
• Flip-Flops – SR, D, JK &T
• Bufffer Register
• Shift Register – SISI,SIPO,PISO,PIPO
• Design of sequential circuits
– State table & State Diagram
• Design of counters
– Modulo-n counter, Johnson, Ring, Up down,
Asynchronous
 Sequential Logic Circuits
• Consists of a combinational circuit to which
memory elements are connected to form a
feedback path.
Inputs Outputs
Combinational
Circuit

Memory
Elements
Sequential Logic Circuits
Combinational Vs Sequential Logic
Circuits
• Combinational Logic circuits - change state
depending upon the actual signals being
applied to their inputs at that time.

• Sequential Logic circuits have some form of

inherent “Memory” built in.
 Sequential Logic Circuits

• Standard logic gates - building blocks of

combinational circuits

• Bi stable latches and flip-flops - building blocks

of sequential logic circuits.
 Sequential Logic Circuits

• Output depends not only on the present value

of its input signals but on the sequence of past
inputs, the input history as well.

• This is in contrast to combinational logic,

whose output is a function of only the present
input.
 Sequential Logic Circuits
• Output state of a “sequential logic circuit” is a
function of the following three states,
– the “present input”,
– the “past input” and/or
– the “past output”.
• Sequential Logic circuits remember these
conditions and stay fixed in their current state
until the next clock signal changes one of the
states, giving sequential logic circuits
“Memory”
 Sequential Logic Circuits
• Two state or bi stable devices
• Have their output or outputs set in one of two
basic states, a logic level “1” or a logic level
“0”
• Will remain “latched” (hence the name latch)
indefinitely in this current state or condition
until some other input trigger pulse or signal
is applied which will cause the bi stable to
change its state once again.
 Sequential Logic Circuits
• “Sequential” means that things happen in a
“sequence”, one after another.
• In sequential logic circuits, the actual clock
signal determines when things will happen
next.
• Simple sequential logic circuits can be
constructed from standard bistable circuits
such as: flip-flops, latches and counters
 Sequential Logic Circuits

Flip-flops, latches and counters can be made by

simply connecting together universal NAND
gates and/or NOR gates in a particular
combinational way to produce the required
sequential circuit.
 Synchronous Clocked Sequential
Circuit

Inputs Outputs
Combinational
circuit

Flip-Flops
Clock Pulses
 Asynchronous Sequential Circuits
• Driven by the inputs levels
• There are no clock pulses.
• The input events drive the circuit.
• In other words, the circuit is said to be
asynchronous if it is not driven by a periodic
clock signal to synchronize its internal states.
Synchronous Vs Asynchronous
Seq. Circuits
 Latches And Flip-Flops
• Latches and Flip-Flops are the basic building
blocks of sequential circuits.
• Bistable devices – 0 state and 1 state.
 Latches and flip-flops
• Basic elements for storing information.

• One latch or flip-flop can store one bit of

information.

• Types of latches and flip-flops: SR, D, JK, and T.

• The major differences in these flip-

flop types are the number of inputs they have
and how they change state.
 Latch Vs. Flip-Flop
• Output of both depends on
– the current inputs &
– previous inputs and outputs.
• Latch does not have a clock signal, whereas
a flip-flop always does.
 Basis for Comparison Latch Flip Flop
Basic principle It follows level triggering approach. Flip flop utilizes edge triggering
approach.
Designed using Logic gates Latches with a clock.

Clock Signal Absent Present

Sensitivity
Power requirement
Operating Speed
Type of operation performed
It is sensitive to applied input It is sensitive to applied input along
signal when enabled. with clock signal.
Less More
Fast Comparatively slow
Asynchronous Synchronous

Circuit analysis Complex Quite easy

Robustness Less Comparatively more

Dependency of operation Its operation depends on present, Here the operation relies on
past input and past output binary present, past input bits and past
values. output along with clock pulses.

Type S-R, J-K, T and D latches. S-R, J-K, T and D Flip flops.

Use as a register Not supported Supported

Required area Less More
 Classification of Sequential Logic

Sequential circuits with loops or feedback paths are said to be “cyclic” in nature.
 Classification of Sequential Logic
1. Event Driven – asynchronous circuits that
change state immediately when enabled.
2. Clock Driven – synchronous circuits that are
synchronised to a specific clock signal.
3. Pulse Driven – which is a combination of the
two that responds to triggering pulses.
 Sequential Logic Circuits
• Apart from two logic states logic level “1” and
logic level “0”, a third element is introduced
that separates sequential logic circuits from
their combinational logic counterparts,
namely TIME.
• Sequential logic circuits return back to their
original steady state once reset.
 Sequential Logic Circuits - Types
• Synchronous and asynchronous
• Synchronous sequential circuits - state of the
device changes only at discrete times in
response to a clock signal.
• Asynchronous circuits - state of the device can
change at any time in response to changing
inputs
 Asynchronous Sequential Circuits
• Sequential circuits are those which use previous and current
input variables by storing their information and placing them back into the
circuit on the next clock (activation) cycle.
• There are two types of input to the combinational logic. External
inputs which come from outside the circuit design are not controlled by
the circuit Internal inputs are functions of a previous output state.
• Asynchronous sequential circuits do not use clock signals as synchronous
circuits do. Instead, the circuit is driven by the pulses of the inputs which
means the state of the circuit changes when the inputs change. Also, they
don’t use clock pulses. The change of internal state occurs when there is a
change in the input variable. Their memory elements are either un-
clocked flip-flops or time-delay elements. They are similar to
combinational circuits with feedback.
 Asynchronous Sequential Circuits
Advantages
• No clock signal, hence no waiting for a clock pulse to begin processing inputs,
therefore fast. Their speed is faster and theoretically limited only by propagation
delays of the logic gates.
• Robust handling. Higher performance function units, which provide average-case
completion rather than worst-case completion. Lower power
consumption because no transistor transitions when it is not performing useful
computation. The absence of clock drivers reduces power consumption. Less
severe electromagnetic interference (EMI).
• More tolerant to process variations and external voltage fluctuations. Achieve high
performance while gracefully handling variable input and output rates and
mismatched pipeline stage delays. Freedom from difficulties of distributing a high-
fan-out, timing-sensitive clock signal. Better modularity.
• Less assumptions about the manufacturing process. Circuit speed adapts to
changing temperature and voltage conditions. Immunity to transistor-to-transistor
variability in the manufacturing process, which is one of the most serious
problems faced by the semiconductor industry
 Asynchronous Sequential Circuits
Disadvantages –
• Some asynchronous circuits may require extra power for certain
operations.
• More difficult to design and subject to problems like sensitivity to the
relative arrival times of inputs at gates. If transitions on two inputs arrive
at almost the same time, the circuit can go into the wrong state depending
on slight differences in the propagation delays of the gates which are
known as race condition.
• The number of circuit elements (transistors) maybe double that of
synchronous circuits. Fewer people are trained in this style compared to
synchronous design. Difficult to test and debug. Their output is uncertain.
• The performance of asynchronous circuits may be reduced in architectures
that have a complex data path. Lack of dedicated, asynchronous design-
focused commercial EDA tools.
 Sequential Feedback Loop
• To retain their current state, sequential
circuits rely on feedback and this occurs when
a fraction of the output is fed back to the
input.

This configuration never changes state because the output will always be the same, either a
“1” or a “0”, it is permanently set.
 SR Flip-Flop
• Most basic sequential logic circuit.
• Basically a one-bit memory bi stable device.
• Has two inputs, one which will “SET” the
device (meaning the output = “1”), and is
labelled S and
• One which will “RESET” the device (meaning
the output = “0”), labelled R.
 SR Flip-Flop
• SR description stands for “Set-Reset”.
• The reset input resets the flip-flop back to its
original state with an output Q.
• Q will be either at a logic level “1” or logic “0”
depending upon this set/reset condition.
• Used in memory circuits to store a single data
bit.
 SR Flip-Flop
• Has three inputs, Set, Reset and its current
output Q relating to it’s current state or
history.
• The term “Flip-flop” relates to the actual
operation of the device, as it can be “flipped”
into one logic Set state or “flopped” back into
the opposing logic Reset state.
NAND Gate SR Latch
NAND Gate SR Latch & Flip-Flop
SR Latch- Set NAND Truth Table

• Let R = 0 & S = 1.
• NAND gate Y at least one input is 0, 𝑄=1.
• Output 𝑄 is fed back to input “A”
• So both inputs to NAND gate X are 1.
• Therefore output Q = 0.
SR Flip Flop - Set

• Let R changes state, and become 1, with S

remaining at 1.
• Now, NAND gate Y inputs are R = 1 and B = 0.
• Since one of its inputs is still 0, 𝑄 remains at 1
and there is no change of state.
• Therefore, the flip-flop is said to be “Latched”
or “Set” with 𝑄= 1 and Q = 0.
SR Latch -Reset State

• Second stable state

• R = 1 and S = 0.
• 𝑄 is at 0, its inverse output at Q is 1.
• NAND gate X has one input as 0. So, Q =1.
• Q is fed back to “B”, so both inputs
to NAND gate Y are 1. Therefore, 𝑄 = 0.
SR Latch -Reset State

• Now, S changes state to 1 with R remaining at

1, Q still remains at 0 and there is no change
of state.
• Therefore, “Reset” state has also been
latched.
Truth Table for Set-
Reset Function
Truth Table for Set-Reset Function
S-R Flip-flop Switching Diagram

0
S-R Flip-flop Switching Diagram
SR FF

• when both S = 1 and R = 1,

outputs Q and 𝑄 can be at either 1 or 0
depending upon the state of the
inputs S or R BEFORE this input condition
existed.
• Therefore the condition of S = R = 1 does not
change the state of the outputs Q and 𝑄.
SR FF

• Input states S = 0 & R = 0 is an undesirable or invalid

condition and must be avoided.
• S = R = 0 causes both Q and 𝑄 to be HIGH.
• But Q is the inverse of 𝑄.
• The result is that the flip-flop looses control
of Q and 𝑄 .
• If the two inputs are now switched HIGH again after
this condition, the flip-flop becomes unstable and
switches to an unknown data state.
 SR Flip Flop
• The unbalance can cause one of the outputs
to switch faster than the other resulting in the
flip-flop switching to one state or the other
which may not be the required state and data
corruption will exist.
• This unstable condition is known as Meta-
stable state.
 SR Flip Flop
• Simple NAND gate SR flip-flop can be set by
applying 0 to its Set input and
• Reset again by then applying 0 to
its Reset input.
• The SR flip-flop is said to be in Meta-stable
condition if both the set and reset inputs are
activated simultaneously.
 Positive NAND Gate SR Flip-flop
• Basic NAND gate SR flip-flop requires 0 inputs
to flip or change state from Q to 𝑄 and vice
versa.
• This basic flip-flop circuit can be modified into
to one that changes state by the application of
positive going input signals with the addition
of two extra NAND gates.
Positive NAND Gate SR Latch
NOR Gate SR Latch
Gated SR Flip-flop
Gated SR Flip-flop
• When Enable input “EN” is 0, outputs of the
two AND gates are also at 0 regardless of the
condition of the two inputs S and R.
• So, Q and 𝑄 will be in their last known state.
• When enable input “EN” becomes 1, the
circuit responds as a normal SR bi stable flip-
flop and the two AND gates becomes
transparent to the Set and Reset signals.
Gated SR Flip-flop
• Enable input can be connected to a clock
timing signal (CLK) adding clock
synchronization to the flip-flop.
• It is called a “Clocked SR Flip-flop“.
• So, a Gated Bistable SR Flip-flop operates as a
standard bistable latch but the outputs are
only activated when 1 is applied to
its EN input and deactivated by a 0.
Disadvantages of SR NAND flip-flop
Two basic switching problems:
1. Set = 0 and Reset = 0 condition (S = R = 0)
must always be avoided
2. If Set or Reset change state while the enable
(EN) input is high, correct latching action may
not occur.
To overcome these two fundamental design
problems, JK flip Flop was developed.
SR Flip Flop
 Excitation Table
• The excitation table has the minimum inputs,
which will excite or trigger the flip flop to go
from its present state to the next state.
• It is derived from the truth table.
• A state table defines the behavior of the sequential
function.
Truth table gives relation between inputs and
outputs.
Excitation table is used for design of flip-flops and
counters.
Truth table contains inputs and excitation table takes
outputs as inputs.
A characteristic table has the control input
(D or T) as the first column, the current state as the
middle column, and the next state as the last
column.
 Sequential Circuits
Differences between a
• Truth table
• State table
• Characteristic table and
• Excitation table
 Truth table
• Explains the functionality of a given element
or logic circuit.
• Does this by giving the output of a logic
circuit/element for all the combinations of the
input variables that are possible.
• Describes the relationship between inputs and
outputs.
• Based on the input combinations, the
response of the circuit can be determined by
using the truth table.
 State table
• Describes the transition that takes place in a
sequential circuit from one state to another
state.
• Represents the relation between the inputs,
the present state, and the next states of a
sequential circuit.
• In a state table, which input results in which
next state for a specific current state is
represented in the form of a table.
• It is the truth table of sequential circuits.
 Characteristic table
• Provides information on the inputs of the logic
circuits, the present state and the next state of
the sequential circuits.
• In a characteristic table, for which particular
input and present state which next state will
result for the provided sequential circuit is
represented.
 Excitation Table
• Excitations represent inputs.
• Provides information about the excitations
that result in a state change of the sequential
circuit from the present to the next state.
• Truth table – relation between input
combinations & outputs
• State table - Describes the transition, which
input results in which next state for a specific
current state
• Characteristic table - which particular input
and present state which next state will result
• Excitation table - information about the
excitations that result in a state change
 JK Flip Flop

• Similar to the SR Flip-flop

• But there is no change in state when both J
and K inputs are LOW.
JK Flip Flop

• Most widely used.

• Basically an SR flip flop with feedback
• Considered to be a universal flip-flop circuit.
• J,K inputs – named after inventor Jack Kilby.
• Operation is exactly the same as SR flip-flop.
• Difference is that the JK flip flop has no invalid
input states even when both inputs are 1.
JK Flip Flop

• Basically a gated SR flip-flop with the addition

of a clock input circuitry.
• Clock input prevents illegal or invalid output
condition when both inputs are 1.
• Due to this additional clocked input, JK flip-
flop has four possible input combinations,
“logic 1”, “logic 0”, “no change” and “toggle”.
JK Flip Flop

• 2-input AND gates of SR FF is replaced by 3-

input NAND gates.
• Third input of each gate is connected to the
outputs at Q and 𝑄.
• This cross coupling allows the previously
invalid condition S = 1 and R = 1 state to
produce a “toggle action” as the two inputs
are now interlocked.
 JK Flip Flop
• If the circuit is “SET", the J input is inhibited by
the “0” status of 𝑄 through the lower NAND gate.

• If the circuit is "RESET", K input is inhibited by the

“0” status of Q through the upper NAND gate.

• Q and 𝑄 are always different. So, they are used

to control the input.

• When both inputs J and K are 1, the JK flip flop

toggles.
JK FF
JK FF
JK FF
 JK Flip Flop
• Basically an SR flip flop with feedback.
• Enables only one of its two input terminals to
be active at any time.
• Thereby it eliminates the invalid condition
seen previously in the SR flip flop.
• When J = K = 1, JK FF acts as T(Toggle) Flip
Flop.
 Race Around Condition
JK Flip flop
• If J=K=1, and if CLK=1 for a long period of time,
then Q output will toggle as long as CLK is high.
• This makes output of the flip-flop unstable or
uncertain.
• This problem is called race around condition in
J-K flip-flop.
• To avoid this, the timing pulse period ( T ) must
be kept as short as possible (high frequency).
 Master Slave JK flip flop
• Eliminates all the timing problems.
• Combination of two JK flip-flops connected
together in a series.
• One acts as the “master” and the other as
a “slave”.
• Output from the master flip flop is connected
to the two inputs of the slave flip flop whose
output is fed back to inputs of the master flip
flop.
Master Slave JK flip flop
 Master Slave JK flip flop

• An inverter is connected to clock pulse in such

a way that the inverted clock pulse is given to
the slave flip-flop.
 Working of master slave flip flop
1. When the clock pulse goes to 1, the slave is
isolated.
2. J and K inputs affect the state of the system.
3. The slave flip-flop is isolated until the CP goes
to 0.
4. When the CP goes back to 0, information is
passed from the master flip-flop to the slave
and output is obtained.
Master
slave FF

5. First, the master flip flop is positive level

triggered and the slave flip flop is negative
level triggered, so the master responds
before the slave.
6. If J=0 and K=1, the high 𝑄 output of the
master goes to the K input of the slave and
the clock forces the slave to reset, thus the
slave copies the master.
Master slave FF
5. If J=1 and K=0, the high Q output of the
master goes to the J input of the slave and
the Negative transition of the clock sets the
slave, copying the master.
6. If J=1 and K=1, it toggles on the positive
transition of the clock and thus the slave
toggles on the negative transition of the
clock.
7. If J=0 and K=0, the flip flop is disabled and Q
remains unchanged.
Timing Diagram of Master Slave
Flip Flop
Master slave FF
1. When the Clock pulse is high the output of
master is high and remains high till the clock
is low because the state is stored.
2. Now the output of master becomes low
when the clock pulse becomes high again
and remains low until the clock becomes high
again.
3. Thus toggling takes place for a clock cycle.
Master slave FF
4. When the clock pulse is high, the master is
operational but not the slave thus the output of the
slave remains low till the clock remains high.
5. When the clock is low, the slave becomes
operational and remains high until the clock again
becomes low.
6. Toggling takes place during the whole process since
the output is changing once in a cycle.
7. This makes the Master-Slave J-K flip flop a
Synchronous device as it only passes data with the
timing of the clock signal.
 SR Flip Flop

D-type Flip Flop

 D-type Flip Flop
• SR flip-flop requires two inputs :“SET” and
“RESET”
• By connecting an inverter (NOT gate) to the SR
flip-flop both “SET” and “RESET” can be done
using single input
• Now the two input signals are complements of
each other.
• This complement avoids the condition that
both inputs are LOW
 D-type Flip Flop
• This single input is called the “DATA” (D) input.
• If D is HIGH, flip flop is “SET”
• If D is LOW, becomes “RESET”.
• Therefore, whenever the input changes, the
output also changes.
• To avoid this, additional input ‘Clk’ is used
• Therefore, ‘D’ input is copied to the
output ’Q’ only when the clock input is active.
 D-type Flip Flop
• The “D flip flop” will store and output
whatever logic level is applied to its data
terminal so long as the clock input is HIGH.
Clk D Q Q’ Description

Memory
↓»0 X Q Q’
no change

↑»1 0 0 1 Reset Q » 0

↑»1 1 1 0 Set Q » 1
 D-type Flip Flop
• This configuration eliminates the invalid inputs
combinations as there cannot be the same
inputs.
• During the clock pulse, D flipflops SET output
when its input is High & Resets when the
input is LOW.
• It is easier to configure as compared to SR Flip
flop because there are no Invalid inputs.
Toggle T-type Flip-flop
 Toggle T-type Flip-flop
• The toggle flip-flop changes state when the
clock input is applied.
• The transition from “0” to “1” will cause the
output to toggle
• Hence called as Toggle FF
• T-FF is the basic building block of many digital
circuits including frequency dividers and
digital counters.
 Toggle T-type Flip-flop
• Output of T-FF changes state on every
application of a clock signal.
• So, its output frequency is one-half that of
the input signal frequency
• Therefore, it acts as a frequency divider.
• By cascading more T-FF together, the output
of the first flip-flop acts as the clock for the
second T FF and the second flip-flop acts as
clock input to the third T-FF, etc, creating a
frequency division.