Unit-IV

Introduction to Sequential circuits and its

applications: Latches, Flipflops, Storage Elements
, Flip-flops: S-R Flip flop, D Flip Flop, J-K Flip Flop, T
Flip flop, master slave JK flip flop, Analysis of Clocked
Sequential Circuits, Flip Flop Conversions
 Introduction
• The sequential circuit is a special type of circuit that has a series of inputs
and outputs.
• The outputs of the sequential circuits depend on both the combination of
present inputs and previous outputs.
• The previous output is treated as the present state. So, the sequential
circuit contains the combinational circuit and its memory storage
elements.
• A sequential circuit doesn't need to always contain a combinational circuit.
So, the sequential circuit can contain only the memory element.
Inputs Combinational Outputs
circuit Flip
Next Flops Present
state
state

Timing signal
(clock)

Clock
a periodic external event (input)

Clock
synchronizes when current state changes happen
keeps system well-behaved
makes it easier to design and build large systems
 Difference between the combinational circuits and
sequential circuits are given below:
S.No Combinational Circuits Sequential Circuits
1 The outputs of the combinational circuit The outputs of the sequential circuits
depend only on the present inputs. depend on both present inputs and
present state(previous output).

2 The feedback path is not present in the The feedback path is present in the
combinational circuit. sequential circuits.
3 In combinational circuits, memory In the sequential circuit, memory
elements are not required. elements play an important role and
require.
4 The clock signal is not required for The clock signal is required for
combinational circuits. sequential circuits.
5 The combinational circuit is simple to It is not simple to design a sequential
design. circuit.
6 Combinational circuits are faster because Sequential circuits are slower than
the delay between the input and the combinational circuits
output is due to propagation delay of
gates only.
Types of Sequential Circuits
 Difference between Synchronous and Asynchronous Sequential
Circuits
Key Synchronous Sequential Circuits
Synchronous sequential circuits are
digital sequential circuits in which
the feedback to the input for next
Definition
output generation is governed by
clock signals.
In Synchronous sequential circuits,
the memory unit which is being get
Memory Unit used for governance is clocked flip
flop.
The states of Synchronous
sequential circuits are always
predictable and thus reliable.
State
Asynchronous Sequential
Circuits
Asynchronous sequential
circuits are digital sequential
circuits in which the feedback
to the input for next output
generation is not governed by
clock signals.
Unclocked flip flop or time
delay is used as memory
element in case of
Asynchronous sequential
circuits.
There are chances for the
Asynchronous circuits to enter
into a wrong state because of
the time difference between
the arrivals of inputs. This is
called "race condition".
Key Synchronous Sequential Circuits Asynchronous Sequential
Circuits
It is easy to design Synchronous The presence of feedback
sequential circuits among logic gates causes
Complexity instability issues making the
design of Asynchronous
sequential circuits difficult.
Due to the propagation delay of Since there is no clock signal
clock signal in reaching all delay, these are fast compared
Performance elements of the circuit the to the Synchronous Sequential
Synchronous sequential circuits Circuits
are slower in its operation speed
Synchronous circuits are used in Asynchronous circuits are used
counters, shift registers, memory in low power and high speed
units. operations such as simple
microprocessors, digital signal
Example
processing units and in
communication systems for
email applications, internet
access and networking.
 Clock Signal and Triggering
Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the same.
When ON time and OFF time of the clock signal are the same, a square wave is used to
represent the clock signal. Below is a diagram which represents the clock signal:

Types of Triggering
These are two types of triggering in sequential circuits:
Level triggering
The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated. There are
the following types of level triggering:
Positive level triggering
In a positive level triggering, the signal with Logic High occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of positive level
triggering:
Negative level triggering
In negative level triggering, the signal with Logic Low occurs. So, in this triggering, the circuit
is operated with such type of clock signal. Below is the diagram of Negative level triggering:

Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition either from
Logic Low to Logic High or Logic High to Logic Low.
Based on the transitions of the clock signal, there are the following types of edge
triggering:
Positive edge triggering
The transition from Logic Low to Logic High occurs in the clock signal of positive edge
triggering. So, in positive edge triggering, the circuit is operated with such type of clock
signal.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative edge
triggering. So, in negative edge triggering, the circuit is operated with such type of clock
signal.
 Applications of Sequential Circuits
• Shift Registers
• Flip Flops
• ADC and DAC converters
• Counters
• Clocks
• Used as registers inside microprocessors and microcontrollers to
store temporary information.
• Applied in programmable devices such as CPLD,PLD and FPGA.
Advantages of Sequential Circuits:

Memory: Sequential circuits have the ability to store binary values, which makes them
ideal for applications that require memory elements, such as timers and counters.
Timing: Sequential circuits are commonly used to implement timing and
synchronization in digital systems, making them essential for real-time control
applications.
State machine implementation: Sequential circuits can be used to implement state
machines, which are useful for controlling complex digital systems and ensuring that
they operate as intended.
Error detection: Sequential circuits can be designed to detect errors in digital systems
and respond accordingly, improving the reliability of digital systems.

Disadvantages of Sequential Circuits:

Complexity: Sequential circuits are typically more complex than combinational circuits
and require more components to implement.
Timing constraints: The design of sequential circuits can be challenging due to the need
to ensure that the timing of the inputs and outputs is correct.
Testing and debugging: Testing and debugging sequential circuits can be more difficult
compared to combinational circuits due to their complex structure and state-dependant
outputs.
 Latches and Flip Flops
• Latches and flip flops are the basic elements and these are used to store
information. One flip flop and latch can store one bit of data.
• The main difference between the latches and flip flops is that, a latch checks
input continuously and changes the output whenever there is a change in
input.
• But, flip flop is a combination of latch and clock that continuously checks
input and changes the output time adjusted by the clock.
• Both Latches and flip flops are circuit elements wherein the output not only
depends on the current inputs, but also depends on the previous input and
outputs.
• The main difference between the latch and flip flop is that a flip flop has a
clock signal, whereas a latch does not. Basically, there are four types of
latches and flip flops: SR, D, JK and T.
 Difference between Latch and Flip flop
SNO Flip-flop Latch
Latch is also a bistable device whose
Flip-flop is a bistable device i.e., it has two
1 states are also represented as 0 and
stable states that are represented as 0 and 1.
1.
It checks the inputs but changes the output It checks the inputs continuously
2 only at times defined by the clock signal or and responds to the changes in
any other control signal. inputs immediately.
3 It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND are
4 These are also made up of gates.
building blocks of flip flops.
They are classified into asynchronous or There is no such classification in
5
synchronous flipflops. latches.
These can be used for the designing
It forms the building blocks of many
6 of sequential circuits but are not
sequential circuits like counters.
generally preferred.
7 Flip-flop always have a clock signal Latches doesn’t have a clock signal
8 Flip-flop can be build from Latches Latches can be build from gates
9 ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch
 Storage Elements
• A storage element in a digital circuit can maintain a binary state
indefinitely, until directed by an input, signal to switch states.
• The major differences among various types of storage elements are
in the number of inputs in the manner in which the inputs affect
the binary state.
• Storage elements that operate with signal levels are referred to as
latches, these are controlled by a clock transitions are referred to as
flip-flop.
• Latches are said to be level sensitive devices, flip-flops are edge
sensitive devices.
 SR Latch
SR Latch is also called as Set Reset Latch.
This circuit has two inputs S & R and two outputs Q & Q’.
The state of the latch corresponds to the level of Q (HIGH or LOW, 1 or
0) and Q’ is, of course.
S-R Latch with NORs (active high S-R latch)
S- R Latch Truth table.

S R 𝑸𝒏 𝑸𝒏+𝟏 State
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
• S-R latch made from cross-coupled NORs
1 0 0 1 Set
• If Q = 1, set state for S=1,R=0
• If Q = 0, reset state for S=0,R=1 1 0 1 1
• Usually S=0 and R=0 no change in state. 1 1 0 x Invalid
• S=1 and R=1 generates 1 1 1 x
𝑸 =Present state
unpredictable/Invalid results 𝑸𝒏 =Next state
𝒏+𝟏
 S-R Latch with NANDs(active-low S-R Latch)
S- R Latch Truth table.
S R 𝑸𝒏 𝑸𝒏+𝟏 State
0 0 0 x Invalid
0 0 1 x
0 1 0 0 Set
0 1 1 0
1 0 0 1 Reset
1 0 1 1
1 1 0 0 No
1 1 1 1 Change
• Latch made from cross-coupled NANDs
• Sometimes called S’-R’ latch
• If Q = 1, set state for S=1,R=0
• If Q = 0, reset state for S=0,R=1
• Usually S=1 and R=1 No change in state.
• S=0 and R=0 generates unpredictable/Invalid results
 SR Flip-Flop
• SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal.
• The type flip-flop which has two inputs namely S (Set) and R (Reset) is termed as
an SR flipflop.
• If the S and R inputs of the flip-flop control its outputs when a clock pulse is present
(i.e. goes from either low to high or high to low), then it called a clocked SR flip-flop.
• Since, the clock signal synchronizes the operation of the SR flip-flop, hence the
clocked SR flip-flop is also known as synchronous SR flip-flop.
 SR Flip-Flop
Characteristic table of SR flip-flop

Prese
Present Next
Clk nt
Inputs State
State
1 S R Qt Qt+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
S R Qt+1 State 1 0 1 1 0
0 0 Qt No change 1 1 0 0 1
0 1 0 Reset 1 1 0 1 1
1 0 1 Set 1 1 1 0 x
1 1 - Invalid 1 1 1 1 x
 S-R Flip Flop Truth table

Present Present Next

Clk S-R Flip Flop Excitation table table
Inputs State State

1 S R Qt Qt+1 Qt Qt+1 S R
1 0 0 0 0 0 0 0 X
1 0 0 1 1 0 1 1 0
1 0 1 0 0 1 0 0 1
1 0 1 1 0 1 1 X 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 x
1 1 1 1 x

Qn+1=S+R′Qn
 D Flip-Flop
• In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0"
and RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:
 Override the feedback latching action.
 Force both outputs to be 1.
 Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.
• The D flip flop is the most important flip flop from other clocked types. It
ensures that at the same time, both the inputs, i.e., S and R, are never equal to
1.
• The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data).
• This single data input, which is labeled as "D" used in place of the "Set" input
and for the complementary "Reset" input, the inverter is used. Thus, the level-
sensitive D-type or D flip flop is constructed from a level-sensitive SR flip flop.
 D Qt+1 State
0 0 Reset
1 1 Set

D Flip Flop Excitation table table

Characteristic table of D flip-flop Qt Qt+1 D

0 0 0
Pres
Present Next 0 1 1
Clk ent
Inputs State
State 1 0 0
1 D Qt Qt+1 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Qn+1=D
 JK Flip-Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:
• When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
• When the Set or Reset input changes their state while the enable input is 1, the
incorrect latching action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop.
• The JK flip flop was named after Jack Kilby, the Texas Instruments engineer that
invented the integrated circuit in 1958.
• The JK flip flop is a universal flip flop having two inputs 'J' and 'K'.
• The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are
prevented by the addition of a clock input circuit.
• The symbol of JK flip flop is the same as SR Bistable Latch except for the addition of a
clock input.
 Characteristic table of JK flip-flop

Prese
Present Next
Clk nt
Inputs State
State
1 J K Qt Qt+1
1 0 0 0 0
1 0 0 1 1
J K Qt+1 State 1 0 1 0 0
0 0 Qt No change 1 0 1 1 0
0 1 0 Reset 1 1 0 0 1
1 0 1 Set 1 1 0 1 1
1 1 Qt Toggle 1 1 1 0 1
1 1 1 1 0
 J-K Flip Flop Truth table

Present Present Next

Clk
Inputs State State
J-K Flip Flop Excitation table table
1 J K Qt Qt+1
1 0 0 0 0 Qt Qt+1 J K
1 0 0 1 1 0 0 0 X
1 0 1 0 0 0 1 1 X
1 0 1 1 0 1 0 X 1
1 1 0 0 1 1 1 X 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Q(n+1) = JQn’ + K’Qn

 Master-Slave JK Flip-Flop
 The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is
changed before the clock input's timing pulse has time to go "Off". We have
to keep short timing plus period (T) for avoiding this period.
 The master-slave flip flop is constructed by combining two JK flip flops.
These flip flops are connected in a series configuration. In these two flip
flops, the 1st flip flop work as "master", called the master flip flop, and the
2nd work as a "slave", called slave flip flop.
 The master-slave flip flop is designed in such a way that the output of the
"master" flip flop is passed to both the inputs of the "slave" flip flop. The
output of the "slave" flip flop is passed to inputs of the master flip flop.
 In "master-slave flip flop", apart from these two flip flops, an inverter
or NOT gate is also used. For passing the inverted clock pulse to the "slave"
flip flop, the inverter is connected to the clock's pulse. In simple words,
when CP set to false for "master", then CP is set to true for "slave", and
when CP set to true for "master", then CP is set to false for "slave".
 T Flip-Flop
• In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this
flip-flop work as a Toggle switch. The next output state is changed with the complement
of the present state output. This process is known as "Toggling"'.
• We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip
Flop" has only one input, which is constructed by connecting the input of JK flip flop. This
single input is called T.
• In simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop".
Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".
Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK
defines the clock signal input.
 T Qt+1 State
0 Qt No change
1 Qt Toggle

T Flip Flop Excitation table table

Characteristic table of T flip-flop Qt Qt+1 T

0 0 0
Pres
Present Next 0 1 1
Clk ent
Inputs State
State 1 0 0
1 T Qt Qt+1 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Q(n+1) = TQn’ + T’Qn = T XOR Qn

 Analysis of Clocked Sequential Circuits
• Analysis describes what a given circuit will do under
certain operating conditions.
• The behavior of a clocked sequential circuit is
determined from the inputs, the outputs, and the
state of its flip-flops.
• The outputs and the next state are both a function of
the inputs and the present state.
• The analysis of a sequential circuit consists of obtaining a
table or a diagram for the time sequence of inputs,
outputs, and internal states.
 Analysis of Clocked Sequential Circuits
• The behavior of a clocked sequential circuit can be
described algebraically by means of state
equations. A state equation (also called a transition
equation ) specifies the next state as a function of
the present state and inputs.
• A state table and state diagram are then presented
to describe the behavior of the sequential circuit
 Analysis of Clocked Sequential Circuits
Consider the
sequential circuit
 Analysis of Clocked Sequential Circuits

• The D input of a flip-flop determines the value of the next

state (i.e., the state reached after the clock transition), it is
possible to write a set of state equations for the circuit:
A(t + 1) = A(t)x(t) + B(t)x(t) B(t + 1) = A’(t)x(t)

• A state equation is an algebraic expression that specifies the

condition for a flip-flop state transition.
• The left side of the equation, with (t + 1), denotes the next
state of the flip-flop one clock edge later.
• The right side of the equation is a Boolean expression that
specifies the present state and input conditions that make the
next state equal to 1.
 Analysis of Clocked Sequential Circuits
• Since all the variables in the Boolean expressions are a function of
the present state, we can omit the designation ( t ) after each variable
for convenience and can express the state equations in the more
compact form
A(t + 1) = Ax + Bx B(t + 1) = A’x
Similarly, the present-state value of the output can be expressed
algebraically as

y(t) = [A(t) + B(t)]x’(t) y = (A + B)x’

Analysis of Clocked Sequential Circuits
State table
Analysis of Clocked Sequential Circuits
State
diagram
Analysis of Clocked Sequential Circuits

• Circuit diagram  Equations State table

 State diagram
 Conversion of Flip-Flops
• For the conversion of one flip flop to another, a

combinational circuit has to be designed first. If a JK Flip

Flop is required, the inputs are given to the combinational
circuit and the output of the combinational circuit is
connected to the inputs of the actual flip flop. Thus, the
output of the actual flip flop is the output of the required
flip flop
 Conversion of Flip-Flops

• SR flip-flop to D flip-flop
• SR flip-flop to JK flip-flop
• JK flip-flop to T flip-flop
 SR flip-flop to D flip-flop
• Here, the given flip-flop is SR flip-flop and the
desired flip-flop is D flip-flop. Therefore, consider
the following characteristic table of D flip-flop

D flip- Present Next State

flop State
input
D Qt Qt+1
0 0 0
0 1 0
1 0 1
1 1 1
SR flip-flop to D flip-flop
SR flip-flop to D flip-flop
SR flip-flop to JK flip-flop
SR flip-flop to JK flip-flop
JK flip-flop to T flip-flop
JK flip-flop to T flip-flop