CH 4 5 Sequinital New

Sequential Circuit
Chapter
Chapt. 4 &5
ECEG122 [Ch-3] Microprocessor and Digital Logic
Content
• Synchronous and Asynchronous Operation
• S-R,J-K,T and D Flip Flops
• State Minimization
• Analysis of Synchronous and Asynchrony Sequential
Circuit
• Design using PLA and PAL
• ADC and DAC Circuit

Sequential Logic
• The logic circuits discussed previously are known as
combinational, in that the output depends only on the condition of
the latest inputs
• However, we will now introduce a type of logic where the output
depends not only on the latest inputs, but also on the condition of
earlier inputs. These circuits are known as sequential, and
implicitly they contain memory elements

Sequential Circuit

Importance of clock signal in sequential circuits
• The clock signal plays a crucial role in sequential circuits.
• A clock is a signal, which oscillates between logic level 0 and logic level 1,
repeatedly.
• Square wave with constant frequency is the most common form of clock signal.
• A clock signal has “edges”. These are the instants at which the clock changes
from 0 to 1 (a positive edge) or from 1 to 0 (a negativeedge).

Importance of clock signal in sequential circuits
• Clock signals control the outputs of the sequential circuit .
• That is it determines when and how the memory elements change
their outputs .
• If a sequential circuit is not having any clock signal as input, the
output of the circuit will change randomly.
• So that they cannot retain their state till the next input signal
arrives.
• But sequential circuits with clock input will retain its state till the
next clock edge occurs.

Classification of sequential circuits
• Based on the clock signal input, the sequential circuits are classified
into two types.
 Synchronous sequential circuit
 Asynchronous sequential circuit

Synchronous sequential circuits
• In Synchronous sequential circuit, the output depends on present
and previous states of the inputs at the clocked instances.
• The circuits use a memory element to store the previous state.
• The memory elements in these circuits will have clocks. All these
clock signals are driven by the same clock signal

• Using clock signal, state changes will occur across all storage
elements.
• These circuits are bit slower compared to asynchronous because
they wait for the next clock pulse to arrive to perform the next
operation.
• These circuits can be clocked or pulsed.
• The Synchronous sequential circuits that use clock pulses in their
inputs are called clocked-sequential circuits. They are very stable.
• The sequential circuits that change their state using the pulse and
these are called pulsed or unclocked sequential circuits.

• Where we use synchronous sequential circuits??
• Used in the design of MOORE-MEALY state management
machines.
• They are used in synchronous counters, flip flops etc.
• Limitations of Synchronous Sequential Circuits
• All the flip – flops in synchronous sequential circuits must be
connected to clock signal. Clock signals are very high frequency
signals and clock distribution consumes and dissipated a large
amount of heat.
• Critical path or the slowest path determines the maximum
possible clock frequency. Hence they are slower than asynchronous
circuits.
•.
Asynchronous Sequential circuits
• The Sequential circuits which do not operate by clock signals are
called “Asynchronous sequential circuits”.
• These circuits will change their state immediately when there is a
change in the input signal .
• The Circuit behavior is determined by signals at any instant in
time and the order in which input signals change.

• They do not operate in pulse mode.
• They have better performance but hard to design due to timing
problems.
• Mostly we use the asynchronous circuits when we require the low
power operations.
• They are faster than synchronous sequential circuits as they do not
need to wait for any clock signal
• DRAWBACKS:
 Asynchronous sequential circuits are more difficult to design.
 Though they have a faster performance, their output is
uncertain

• Where we use Asynchronous sequential circuits?
• These are used when speed of operation is important. As they are
independent of internal clock pulse, they are operate quickly. so
they are used in Quick response circuits.
• Used in the communication between two units having their own
independent clocks.
• Used when we require the better external input handling.

Asynchronous Vs. synchronous
• Asynchronous sequential circuits • Synchronous sequential circuits
• If some or all the outputs of a sequential circuit • If all the outputs of a sequential circuit change (affect) with
do not change (affect) with respect to active respect to active transition of clock signal, then that sequential
transition of clock signal, then that sequential circuit is called as Synchronous sequential circuit.
circuit is called as Asynchronous sequential • That means, all the outputs of synchronous sequential circuits
circuit. change (affect) at the same time.
• That means, all the outputs of asynchronous • Therefore, the outputs of synchronous sequential circuits are in
sequential circuits do not change (affect) at the synchronous with either only positive edges or only negative
same time. edges of clock signal
• Therefore, most of the outputs of asynchronous • In synchronous circuits the input are pulses (or levels and
sequential circuits are not in synchronous with
pulses) with certain restrictions on pulse width and circuit
either only positive edges or only negative edges
of clock signal. propagation delay. Therefore synchronous circuits can be
• The circuit is considered to be asynchronous if it divided into clocked sequential circuits and uncklocked or
does not employ a periodic clock signal C to pulsed sequential circuits
synchronize its internal changes of state. Therefore • On the other hand in an unclocked or pulsed sequential circuit,
the state changes occur in direct response to signal such a clock is not present. Pulse mode circuits require two
changes on primary (data) input lines, and different consecutive transitions between 0 and 1 - that is a 0-pulseor a 1
memory elements can change state at different pulse to alter the circuit’s state. A pulse -mode circuit is designed
times. to respond to pulses of certain duration; the constant signals
• In asynchronous sequential circuits the inputs are between the pulses are “null” or “spacer” signals, which do not
levels and there are no clock pulses; the inputs affect the circuit’s behavior
events drive the circuit.

Feedback in Sequential Circuits
• Combinational circuits do not require any feed back as the outputs are purely dependent
on the present value of the input.
• But in case of sequential circuits, the outputs are dependent on past values of the
input along with present values.
• In order to involve memory element like a flip – flop, feedback must be introduced in the
circuit.
• For example, consider a simple feedback circuit as shown below
• If 0 is the input to the inverter at an instance, this 0 will propagate and the output is
1. This 1 is fed back as input. This 1 will propagate and the output is 0. The process
repeats and the result is a continuous oscillation of output between 0 and 1. There is
no stable state in this scenario.
• Now consider the following example of two inverters connected as shown

Feedback in Sequential Circuits
• Here two inverters are connected back to back with the output of the
second inverter fed back to input of first inverter.
• If 0 is the input to first inverter at an instance, it propagates through
the first inverter and the output is 1.
• This 1 is input to second inverter and propagates through it. The
output of the second inverter is 0 which is fed back to the first
inverter. But the input to first inverter is already 0 and hence no
change occurs.
• The circuit is said to be in a stable circuit. Another stable state can be
obtained when the input to the first inverter is 1

Lathes and Flip flops

Latches flip-flops and Bistables
• A memory stores data – usually one bit per element
• A snapshot of the memory is called the state
• A one bit memory is often called a bistable,
 i.e., it has 2 stable internal states
• Flip-flops and latches are particular implementations of bistables
• Next page explain the Diagram(Bistable)

Bistable Element
• The simplest sequential circuit or storage element is a bistable element,
• which is constructed with two inverters connected sequentially in a loop as
shown in Figure .
• It has no inputs and two outputs labeled Q and Q’.
• Since the circuit has no inputs, we cannot change the values of Q and Q’.
However, Q will take on whatever value it happens to be when the circuit is first
powered up.
• Assume that Q = 0 when we switch on the power. Since Q is also the input to the
bottom inverter, Q’, therefore, is a 1. A 1 going to the input of the top inverter will
produce a 0 at the output Q, which is what we started off with. Similarly, if we
start the circuit with Q = 1, we will get Q’ = 0, and again we get a stable situation.

Latches and flip-flops
• Latches and flip-flops are the basic elements for storing information.
• One latch or flip-flop can store one bit of information.
• The main difference between latches and flip-flops is that for latches, their
outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their content changes immediately
when their inputs change.
• Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock
signal. After the rising or falling edge of the clock, the flip-flop content remains
constant even if the input changes.
• There are basically four main types of latches and flip-flops: SR, D, JK, and T.
• The major differences in these flip-flop types are the number of inputs they have
and how they change state.
• For each type, there are also different variations that enhance their operations.

SR Latch
• An SR latch is a memory element with 2inputs: Reset (R) and Set
(S) and 2 outputs: Q and Q .
• We can implement S-R latch using NAND or NOR Gate

SR Latch - Operation
• R = 1 and S = 0
 Gate 1 output in ‘always 0’ condition, Q=0
 Gate 2 in ‘complement’ condition, so Q=0
• This is the (R)eset condition

• S = 0 and R to 0
 Gate 2 remains in ‘complement’ condition, Q = 1
 Gate 1 into ‘complement’ condition, Q = 0
• This is the hold condition

• S = 1 and R = 0
 Gate 1 into ‘complement’ condition, Q =1
 Gate 2 in ‘always 0’ condition, Q = 0
• • This is the (S)et condition

• S = 1 and R = 1
Gate 1 in ‘always 0’ condition, Q = 0
 Gate 2 in ‘always 0’ condition, Q = 0
• • This is the illegal condition

SR Latch (NAND version)
0 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
Q’ 0
1 0
1 R’ 1 1
X Y NAND
00 1
01 1
10 1
11 0
2024.01.01 Sequential Circuits PJF - 27
1 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
Q’ 0
1 0
1 R’ 1 1 1 0 Hold
X Y NAND
00 1
01 1
10 1
11 0
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
X Y NAND
00 1
01 1
10 1
11 0
1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0
Relation between NAND and time diagram
• If both S' and R' are asserted, then both Q and Q' are equal
to 1 as shown at time t4. If one of the input signals is de-
asserted earlier than the other, the latch will end up in the
state forced by the signal that was de-asserted later as
shown at time t5. At t5, R' is de-asserted first, so the latch
goes into the normal set state with Q = 1 and Q' = 0.
• A problem exists if both S' and R' are de-asserted at
exactly the same time as shown at time t6. If both gates
have exactly the same delay then they will both output a 0
at exactly the same time. Feeding the zeros back to the
gate input will produce a 1,
• again at exactly the same time, which again will produce a
0, and so on and on. This oscillating behavior, called the
critical race, will continue forever. If the two gates do not
have exactly the same
• delay then the situation is similar to de-asserting one input
before the other, and so the latch will go into one state or
the other. However, since we do not know which is the
faster gate, therefore, we do not know which state the
latch will go into. Thus, the latch’s next state is
undefined.

Transparent D Latch
• The disadvantage with the SR latch is that we need to ensure that the two inputs,
S and R, are never de-asserted
• at the same time. This situation is prevented in the D latch by adding an inverter
between the original S and R inputs
• We now modify the SR Latch such that its output state is only permitted to change
when a valid enable signal (which could be the system clock) is present
• This is achieved by introducing a couple of AND gates in cascade with the R and
S inputs that are controlled by an additional input known as the enable (EN) input.
• and replacing them with just one input D (for data) as shown in Figure (a) and (b).

D Latch
• Notice that the placement of the inverter with respect to the Q output
is such that the Q output value follows the D input. This feature is
useful because, whereas the SR latch is useful for setting or resetting
a flag on a given condition,
• the D latch is useful for simply storing a bit of information that is
presented on a line. Figure 8(c) shows the truth table for the D latch,
and Figure 8(d) shows the graphic symbol.

D Latch with Enable
• Just like the SR latch with an enable input, the D latch can also have an enable input as shown
in Figure9(a).
• When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the
latch is said to be “open” and the path from the input D to the output Q is “transparent ”.
• Hence the circuit is often referred to as a transparent latch. When E is de-asserted (E = 0), the
latch is disabled or “closed”, and the Q output retains its last value independent of the D input.
A sample timing diagram for the operation of the D latch with enable is shown in Figure9(d).
Between t0 and t1, the latch is enabled with E = 1 so the output Q follows the input D.
Between t1 and t2, the latch is disabled, so Q remains stable even when D changes.

Transparent D Latch
• See from the AND truth table:

 if one of the inputs, say a is 0, the output is always 0
 Output follows b input if a is 1
• The complement function ensures that R and
S can never be 1 at the same time, i.e., illegal avoided
Transparent D Latch
• See Q follows D input provided EN=1. If EN=0, Q maintains previous state

Flip flops

Logic Symbol
• The logic or graphical symbol describes the flip-flop’s inputs and outputs, the names given to
these signals, and whether they are active high or low.
• All the flip-flops have Q and Q' as their outputs. All of them also have a CLK input.
• The small triangle at the clock input indicates that the circuit is a flip-flop and so it is
triggered by the edge of the clock signal; if there is a circle in front, then it is the falling
edge, otherwise, it is the rising edge of the clock signal.
• Without the small triangle, the circuit is a latch. In addition, the flip-flops have one or two
more inputs that characterize the flip-flop and give it its name .

Type of flip Flop
• There are basically four main types of flip-flops: SR, D, JK, and T.
• However, J-K FFs are a lot more complex to build than D-types and so have fallen out
of favor in modern designs, e.g., for field programmable gate arrays (FPGAs) and VLSI
chips
• The major differences in these flip-flop types are in the number of inputs they have and
how they change state.
• Each type can have different variations such as active high or low inputs, whether they
change state at the rising or falling edge of the clock signal, and whether they have
asynchronous inputs or not.
• The flip-flops can be described fully and uniquely by its logic symbol(Block Diagram),
characteristic table, characteristic equation, state diagram, or excitation table ,

SR Flip-Flop
• Like SR latches, SR flip-flops are useful in control applications
where we want to be able to set or reset the data bit.
• However, unlike SR latches, SR flip-flops change their content only
at the active edge of the clock signal. Similar to SR latches, SR flip-
flops can enter an undefined state when both inputs are asserted
simultaneously.

S-R Flip Flop
• Operation

J-K Flip-Flop
• The J-K FF is similar in function to a clocked RS FF, but
with the illegal state replaced with a new ‘toggle’ state
• Where Q’ is the next state and Q is the current state

JK Flip-Flop
• JK flip-flops are very similar to SR flip-flops. The J input is just like the S input in
that when asserted, it sets the flip-flop. Similarly, the K input is like the R input
where it clears the flip-flop when asserted. The only difference is
• when both inputs are asserted. For the SR flip-flop, the next state is undefined,
whereas, for the JK flip-flop, the next state is the inverse of the current state. In
other words, the JK flip-flop toggles its state when both inputs are asserted. The
circuit, truth table and the logic symbol for the JK flip-flop is shown in Figure 17.

T Flip Flop
• The T flip-flop has one input in addition to the clock.
• T stands for toggle for the obvious reason. When T is asserted (T = 1), the flip-flop
state toggles back and forth, and when T is de-asserted, the flip-flop keeps its
current state.
• The T flip-flop can be constructed using a D flip-flop with the two outputs Q and
Q' feedback to the D input through a multiplexer that is controlled by the T input
as shown in Figure 18.

T Flip-Flop
• This is essentially a J-K FF with its J and K inputs connected
together and renamed as the T input
Where Q’ is the next state and Q is the current state

T Flip Flop
• The T flip-flop has one input in addition to the clock.
• T stands for toggle for the obvious reason. When T is asserted (T = 1), the flip-
flop state toggles back and forth, and when T is de-asserted, the flip-flop keeps its
current state.
• The T flip-flop can be constructed using a D flip-flop with the two outputs Q and
Q' feedback to the D input through a multiplexer that is controlled by the T input
as shown in Figure 18.

D Flip-Flop
• A commonly desired function in D flip-flops is the ability to hold the last value
stored rather than load in a new value at the clock edge. This is accomplished by
adding an enable input called EN or CE (clock enable) through a multiplexer as
shown in Figure a.
• When EN = 1, the primary D signal will pass to the D input of the flip-flop, thus
updating the content of the flip-flop. When EN = 0, the bottom AND gate is enabled
and so the current content of the flip-flop, Q, is passed back to the input, thus,
keeping its current value. Notice that changes to the flip-flop value occur only at the
rising edge of the clock. The truth table and the logic symbol for the D flip-flop with
enabled is shown in (b) and (c) respectively.

D Flip Flop
• Operation

Applications of Flip-Flops
• Counters
 A clocked sequential circuit that goes through a predetermined sequence of states
 A commonly used counter is an n-bit binary
• Memories, e.g.,
 Shift register
• Parallel loading shift register : can be used for parallel to serial conversion in serial data communication
• Serial in, parallel out shift register: can be used for serial to parallel conversion in a serial data communication system.
Example: Generally, we come across many counters in our daily life to count the
number of objects .For example to count the number of audience entering or
leaving an auditorium or to count number of vehicles in parking. In this when
any person enters in to auditorium the counter increments its value depending
on its present value. Similarly, it decrements its value depending on its previous
and present value. So Counter retains the present state of the counter to do next
operation.

Design the counter using flip Flop




Other Ways to Implement Combinational Logic
programmable array logic (PAL)

• ROM (read Only Memory): ROM is nothing but the combination
of decoder and Encoder. It is a semi conductor memory and which is
a permanent memory, ROM can also be defined as a Simple Code
conversion unit
 ROM = Fixed AND, Programmable OR

 PAL = Programmable AND, Fixed OR
 PLA = Programmable AND, Programmable OR.

• We have seen how combinational logic can be
implemented using logic gates,
e.g., AND, OR etc.
• However, it is also possible to generate combinational
logic functions using memory devices, e.g., Read Only
Memories (ROMs)

ROM Example
• A ROM is a data storage device:
 Usually written into once (either at manufacture or using a programmer)
 Read at will
 Essentially is a look-up table, where a group of input lines (say n) is used to
specify the address of locations holding m-bit data words
 For example, if n = 4, then the ROM has 24 = 16 possible locations. If m = 4,
then each location can store a 4-bit word So, the total number of bits stored is
m *2n i.e., 64 in the example (very small!) ROM

• Design amounts to putting minterms in the
appropriate address location
• No logic simplification required
• Useful if multiple Boolean functions are to be
implemented, e.g., in this case we can easily
do up to
• 4, i.e., 1 for each output line Reasonably
efficient if lots of minterms need to be
generated

ROM Implementation
• Can be quite inefficient, i.e., become large in size with
only a few non-zero entries, if the number of minterms in
the function to be implemented is quite small
• Devices which can overcome these problems are known
as programmable array logic (PAL)
• In PALs, only the required minterms are generated using a
separate AND plane. The outputs from this plane are
ORed together in a separate OR plane to produce the final
output

ROM Implementation
Programmed by
selectively removing
connections in the AND
and OR planes –
controlled by fuses or
memory bits

Summary

Summary

Review Question
1. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
a) XOR or XNOR gates b) NOR or NAND gates c) AND or OR gates d) AND or NOR gates
Answer B
2. For a D flip-flop, the next state is always equal to the D input . a) True b)
False Answer A
3. Which flip flop cannot accept two logic 1's on the inputs?
a) D Type b) T Type c) JK Type d) SR Type
Answer D
4. The JK flip-flop is in its set mode when input J = -------.and input K = ------.
a) J = 0 and K = 0 b) J = 0 and K = 1 c) J = 1 and K = 0 d) J = 1 and K = 1
Answer C
5.

CH 4 5 Sequinital New

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH 4 5 Sequinital New

Uploaded by

Copyright:

Available Formats

Sequential Circuit

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

• Next page explain the Diagram(Bistable)

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

• • This is the (S)et condition

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

• See from the AND truth table:

• See Q follows D input provided EN=1. If EN=0, Q maintains previous state

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

• Where Q’ is the next state and Q is the current state

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

Where Q’ is the next state and Q is the current state

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

 ROM = Fixed AND, Programmable OR

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic

ECEG122 [Ch-3] Microprocessor and Digital Logic