Sequential Logic in

Encoders and
Decoders
Lague, Silao and Atencio
 01
Encoders
What is it?
 Encoders

• A sequential device that converts input signal into a

coded output signal.
• Digital circuits that take a set of binary inputs and
convert them into a unique binary code.
• Commonly used in digital systems to convert a parallel
set of inputs into a serial code.
 02
Decoders
What is it?
 Decoders
• a logic circuit that changes coded inputs into coded
outputs.
• can be used to implement combinational circuits,
Boolean functions, and convert a digital signal into an
analog signal.
• used in a variety of devices, such as televisions, radios,
and computers.
Clock Circuit Sequential Logic
● Uses flip-flops or gated latches as memory elements.
● The circuit's operation is controlled by a periodic clock pulse that
synchronizes all internal state changes.
● Generates a sequence of repetitive pulses called the clock signal
which is distributed to all the memory elements in the circuit.
Clock Circuit Sequential Logic Encoder
● Uses flip-flops or gated latches as memory elements.
● The circuit's operation is controlled by a periodic clock pulse that
synchronizes all internal state changes.
● Generates a sequence of repetitive pulses called the clock signal
which is distributed to all the memory elements in the circuit.
Clock Circuit Sequential Logic
● Uses flip-flops or gated latches as memory elements.
● The circuit's operation is controlled by a periodic clock pulse that
synchronizes all internal state changes.
● Generates a sequence of repetitive pulses called the clock signal
which is distributed to all the memory elements in the circuit.
On & Off Delayed
Timer Relay
Sequential Logic
 On Delayed Timer Relay

• A timing device that keeps contacts open or closed until a

preset time has passed.
• Used in applications where it is important to ensure that a
circuit is not activated until after a certain amount of time
has elapsed.
• Have their delay action when they are energized and
revert to their original condition instantly upon de-
energization.
On Delayed Timer Relay

• A timing device that keeps contacts open or closed

until a preset time has passed.
• Used in applications where it is important to ensure
that a circuit is not activated until after a certain
amount of time has elapsed.
• Have their delay action when they are energized and
revert to their original condition instantly upon de-
energization.
 On Delayed Timer Relay

• A timing device that keeps contacts open or closed until a

preset time has passed.
• Used in applications where it is important to ensure that a
circuit is not activated until after a certain amount of time
has elapsed.
• Have their delay action when they are energized and
revert to their original condition instantly upon de-
energization.
 Off Delayed Timer Relay

• A type of time delay relay that opens or closes a circuit

when power is removed.
• When energized, off-delay timers change their original state
instantly, but delay their action when the coil is de-
energized.
• Often called "delay on break" timers.
• Can be used to delay the stopping of a motor, which is often
used in commercial and industrial applications
Off Delayed Timer Relay

• A type of time delay relay that opens or closes a circuit when

power is removed.
• When energized, off-delay timers change their original state
instantly, but delay their action when the coil is de-energized.
• Often called "delay on break" timers.
• Can be used to delay the stopping of a motor, which is often
used in commercial and industrial applications
 Off Delayed Timer Relay

• A type of time delay relay that opens or closes a circuit

when power is removed.
• When energized, off-delay timers change their original state
instantly, but delay their action when the coil is de-
energized.
• Often called "delay on break" timers.
• Can be used to delay the stopping of a motor, which is often
used in commercial and industrial applications
SR Flip-flop Sequential Logic
● A basic sequential logic circuit type of flip-flop.
● Can be designed by cross-coupling NAND or NOR
gates. The internal structure of an SR flip-flop
consists of two cross-coupled NOR gates, which
form a basic latch.

Here's how an SR flip-flop operates:

 The SET input 'S' sets the device or generates the
output as 1.
 The RESET input 'R' resets the device or generates
the output as 0.
 When S=0 and R=0, the circuit is in an
indeterminate state, where the outputs are
unpredictable.
 This should be avoided in normal operation, but is
likely to happen when power is first applied.
SR Flip-flop Sequential Logic

● A basic sequential logic circuit type of flip-flop.

● Can be designed by cross-coupling NAND or NOR gate
structure of an SR flip-flop consists of two cross-couple
which form a basic latch.

Here's how an SR flip-flop operates:

 The SET input 'S' sets the device or generates the output
 The RESET input 'R' resets the device or generates the o
 When S=0 and R=0, the circuit is in an indeterminate st
outputs are unpredictable.
 This should be avoided in normal operation, but is likely
power is first applied.
SR Flip-flop Sequential Logic
● A basic sequential logic circuit type of flip-flop.
● Can be designed by cross-coupling NAND or NOR
gates. The internal structure of an SR flip-flop
consists of two cross-coupled NOR gates, which
form a basic latch.

Here's how an SR flip-flop operates:

 The SET input 'S' sets the device or generates the
output as 1.
 The RESET input 'R' resets the device or generates
the output as 0.
 When S=0 and R=0, the circuit is in an
indeterminate state, where the outputs are
unpredictable.
 This should be avoided in normal operation, but is
likely to happen when power is first applied.
D Type Flip-flop Sequential Logic
• A basic building block of sequential logic circuits.

• Has two stable states and can store one bit of state

information.

• Has an input data pin (D), a clock pin (CK), and an output data

pin (Q).
D Type Flip-flop Sequential Logic
Features:
 D input: A single input that sets and resets outputs.
 Clock input: A rising edge of the clock signal causes the flip-
flop to latch input data and transfer it to Q
 Output data pin: Q, which is the inverse of Q
 Control inputs: One or more inputs that change the output state
 Control inputs options: PR (Preset) and CLR (Clear)
 PR: Presets the output to 1
 CLR: Clears the output to 0
 Inverter: Prevents the S and R inputs from being at the same
logic level
 Clock pulse: Uses the symbols ↓ and ↑ to indicate the direction
of the clock pulse
D Type Flip-flop Sequential Logic
Used As:

 Frequency dividers

 Data latches

 Delay flip-flops
D Type Flip-flop Sequential Logic

Used As:

 Frequency dividers

 Data latches

 Delay flip-flops
D Type Flip-flop Sequential Logic
Used As:

 Frequency dividers

 Data latches

 Delay flip-flops
 JK Flip-flop Sequential Logic
● A basic building block of sequential logic
circuits.
● A circuit that has two stable states and can
store one bit of state information.
● The output changes state by signals applied
to one or more control inputs.
JK Flip-flop Sequential Logic

● A basic building block of sequential logic circuits.

● A circuit that has two stable states and can store one bit of state
information.
● The output changes state by signals applied to one or more control inputs.
 JK Flip-flop Sequential Logic
● A basic building block of sequential logic
circuits.
● A circuit that has two stable states and can
store one bit of state information.
● The output changes state by signals applied
to one or more control inputs.
CMOS Flip-flop Sequential Logic
• a logic circuit involving feedback –
the output of a gate drives its input,
primarily via other gates.
• A flip-flop is a logic circuit that uses
feedback.
• Can store state information and
change state when signals are
applied to control inputs.
CMOS Flip-flop Sequential Logic
Encoder
• a logic circuit involving feedback –
the output of a gate drives its input,
primarily via other gates.
• A flip-flop is a logic circuit that uses
feedback.
• Can store state information and
change state when signals are
applied to control inputs.
CMOS Flip-flop Sequential Logic
• a logic circuit involving feedback –
the output of a gate drives its input,
primarily via other gates.
• A flip-flop is a logic circuit that uses
feedback.
• Can store state information and
change state when signals are
applied to control inputs.
Counters Sequential Logic
• A sequential logic circuit that can count input pulses
and accumulate them.
• used in digital electronics for counting purposes.
• Counts specific events happening in the circuit,
such as clock pulses.
• perform various tasks such as frequency division
and timing.
Counters Sequential Logic Encoder
• A sequential logic circuit that can count input pulses
and accumulate them.
• used in digital electronics for counting purposes.
• Counts specific events happening in the circuit,
such as clock pulses.
• perform various tasks such as frequency division
and timing.
Counters Sequential Logic
• A sequential logic circuit that can count input pulses
and accumulate them.
• used in digital electronics for counting purposes.
• Counts specific events happening in the circuit,
such as clock pulses.
• perform various tasks such as frequency division
and timing.
Down Counter Sequential Logic
• a sequential circuit that counts down from a
maximum value to zero, and repeats.
• The count sequence is (2^n-1),…,2,1,0,
where n is the number of bits in the counter.
Down Counter Sequential Logic
• a sequential circuit that counts down from a
maximum value to zero, and repeats.
• The count sequence is (2^n-1),…,2,1,0,
where n is the number of bits in the counter.
Down Counter Sequential Logic
• a sequential circuit that counts down from a
maximum value to zero, and repeats.
• The count sequence is (2^n-1),…,2,1,0,
where n is the number of bits in the counter.
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