Ch3: Sequential logic circuits

and memory elements

Lecture 1: Sequential circuits and Latches

Content Reference: M. Morris Mano, and Michael D. Ciletti, “Digital Design with an introduction to Veilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson, 2017
Note: Reference to images may be found as hyperlinks or in slide notes
What is in this chapter?
• Latches
• SR latch
• D latch
• Flip flops
• D flip-flop
• Gated, edge triggered and Master-slave operation
• JK flip flop
• T flip-flop
• Registers
• Serial/Parallel conversion
• Codes-Error detection and correction
Lecture Hours Laboratory Hours Assignment Hours
6 3 3
Chapter Objectives?
• Know how to distinguish a sequential circuit from a combinational circuit.
• Understand the functionality of a SR latch, transparent latch, D flipflop, JK flip-flop, and T
flip-flop.
• Know how to use the characteristic table and characteristic equation of a flip-flop.
• Understand the HDL models of latches and flip-flops.
• Understand the use, functionality, and modes of operation of registers, shift registers,
and universal shift registers.
• Know how to properly create the effect of a gated clock.
• Understand the structure and functionality of a serial adder circuit.
• Be able to write structural and behavioral HDL models of registers, shift registers and
universal shift registers.
• Know how to use a Hamming code to detect and correct a single error, and to detect a
double error.
What is in this lecture?
• Introduction
• Sequential circuits
• Synchronous Sequential Circuits
• Asynchronous Sequential Circuits
• Storage elements
• Latches
• SR latch
• D latch
Outline
Introduction
📷
💻
• Digital devices such as phones and computers can,
• send, receive, store, retrieve, and process information in binary format 🎥
• To be able to do this they need to be able to store (have memory)
• Up to now you have seen combinational circuits

Combinational circuit: output depends only and immediately on

their inputs

• Sequential circuits can,

• Act as storage elements
• Be used memory
Sequential Circuits
• They are basically combinational connected to memory elements

Inputs Outputs
Combinational
circuit Memory
elements

Block diagram of sequential circuit [1]

Sequential Circuits
• They are basically combinational connected to memory elements
• They are connected via a feedback path

Inputs Outputs
Combinational
circuit Memory
elements

Block diagram of sequential circuit [1]

Sequential Circuits
• They are basically combinational connected to memory elements
• They are connected via a feedback path
• They have a state
• State: “The binary information stored in these elements at any given time”
Store binary
information

Inputs Outputs
Combinational
circuit Memory
elements

Block diagram of sequential circuit [1]

Sequential Circuits
• They are basically combinational connected to memory elements
• They are connected via a feedback path
• They have a state
• State: “The binary information stored in these elements at any given time”
• Have external inputs,
• To receive binary information
• To determine the condition for changing the state

External
inputs
Sequential Circuits (Outputs)
• Not just a function of inputs
• They are a function of,
• Inputs and
• Present State of storage elements

Present State
Sequential Circuits (Next State)
• Next State is also a function of,
• Inputs and
• Present State of storage elements

Next State

Present State
Sequential vs Combinational logic
• A sequential circuit is specified by a time sequence of inputs, outputs,
and internal states
• The outputs of combinational logic depend on only the present
values of the inputs
Types of Sequential Circuits Analogies

📱
📧
• Synchronous sequential circuit: Is a system
whose behavior can be defined from the
📷 Happens one
after other
knowledge of its signals at discrete instants
of time
• Asynchronous sequential circuit: Depends
upon the input signals at any instant of time
and the order in which the inputs change 🎙📢 Happens
continuously
Synchronous Circuits
• Synchronous sequential circuit uses clock signal.
• The clock is commonly denoted by clk.
e.g.: Full adder circuit with a storage element.

Train of clock pulses

1
5
Flip-flops
• Synchronous sequential circuits uses flip-flops as storage element.

1
6
Asynchronous sequential circuit design

• The output depends on

• input signal at a given time,
• the order in which input changes.

• Asynchronous sequential circuits uses time-delay devices, as storage

elements.

1
7
Asynchronous Sequential Circuits
• Asynchronous Sequential Circuits
• Uses time delay devices for storage
• Hard to design due to instability problem
Time delay devices In Asynchronous Circuits
• Storage capability depends on time it takes for signal to propagate
• Alternative to a time-delay device
• Internal propagation delay of logic gates is of sufficient duration
• Gate-Type Asynchronous circuits:
• Use internal propagation delay of logic gates
• Basically a combinational circuit with feedback
• Feedback among logic gates causes instability
Storage elements
There are two types of storage elements, which are
• Latches
• Flip-flops

Latches Flip-flops.
Storage elements that Storage elements that operates
operates with signal levels. with signal transitions.
Level sensitive devices. Edge sensitive devices.
Can be constructed from logic Can be constructed from latches.
gates.
Used in asynchronous Used in synchronous sequential
sequential circuit design circuit design
7
Storage Elements
• A storage element in a digital circuit can maintain a binary state
indefinitely.
• Given, power is delivered to the circuit
• Until, directed by an input signal to switch states
• Storage elements differ based on,
• Number of inputs they possess
• Manner in which input affects binary state
Latches
“Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches”
• In contrast, those controlled by a clock transition are flip-flops
• Latches are the basic circuits from which all flip-flops are constructed
• Uses:
• Storing binary information
• Design of asynchronous sequential circuits
• They are not practical for use as storage elements in synchronous
sequential circuits
NOR SR Latch
• When output Q=1 and Q’=0 latch is said to be in the R Q
set state
• When output Q=0 and Q’=1 latch is said to be in the Q’
S
reset state
• If both inputs are then switched to 0 simultaneously,
S R Q Q’
the device will enter an unpredictable /undefined
1 0 1 0
state /meta-stable state 0 0 1 0 (After SR = 10)
0 1 0 1
0 0 0 1 (After SR = 01)
1 1 0 0 (forbidden)
Function Table
NAND SR Latch (S’R’ Latch)
• SR latch can be constructed from two NAND gates S
also Q

• Comparing the excitation function of the NOR SR

latch we note that S has been replaced with S’ and R
Q’

R with R’
• Hence, the input variables for the NAND SR latch S R Q Q’
1 0 0 1
require the complemented values of those used in
1 1 0 1 (After SR = 10)
the NOR SR latch 0 1 1 0
• For this reason the NAND SR latch is sometimes 1 1 1 0 (After SR = 01)

referred to as an S’R’ latch (or 𝑆ҧ − 𝑅ത latch) 0 0 1 1 (forbidden)

Function Table
 S
Q

SR Latch with Control Input En

Q’
R
• The additional input En, determines when S or R
can affect the output En S R Next state of Q
• It achieves this as, 0 X X No Change
1 0 0 No Change
• En=0 makes S or R input irrelevant as it is a NAND
1 0 1 Q=0; reset state
gate
1 1 0 Q=1; set state
• En=0 makes the outputs of additional NAND gates 1, 1 1 1 Indeterminate
which provides quiescent condition for the SR latch
Function Table
• When all go to 1s state becomes indeterminate
• Even if En goes back to 0 cannot conclusively
determine next state
D Latch (Transparent Latch)
• D latch eliminate undesirable condition in SR latch.
• Make sure S and R never go to 1
• That is S=1 → R=0; R=1 → S=0. ! A not gate

S
Q

En

Q’
R
D Latch (Transparent Latch) cont…
• D latch eliminate undesirable condition in SR latch.
• Make sure S and R never go to 1
• That is S=1 → R=0; R=1 → S=0. ! A not gate
• But S=0, R=0 case? We have En for that

D
Q

En

Q’
D Latch (Transparent Latch) cont…
• Suited for use as a temporary storage for binary information
• Input present at D is transferred to Q output when the enable is
asserted
• Thus, called transparent latch
D
En D Next state of Q
Q
0 X No Change
En 1 0 Q=0; reset state
Q’ 1 1 Q=1; set state

Logic Diagram Function Table

Graphical symbols for latches

NOR SR Latch NAND SR Latch/ D Latch

S’R’ Latch
Graphic symbols for latches [1]
References
[1] M. Morris Mano, and Michael D. Ciletti, “Digital Design with an
introduction to Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson, 2017 – Chapter 5
[2] Mano, M. and Ciletti, M., 2007. “Asynchronous Sequential Logic”, in
Digital Design. 4th ed. London: Prentice-Hall International.