Week 11

Sequential Logic Circuits

Week 11: Sequential Logic Circuits

Learning Outcomes
1. Discuss the importance of sequential logic circuits.
2. Examine the behavior of the building blocks of sequential circuits
3. Determine the future output of a latch or a flip-flop, given its input signals.
4. Differentiate synchronous from asynchronous sequential circuits.
Week 11: Sequential Logic Circuits

Sequential Circuits
• Has memory
• State variables – a set of bits containing all the information about the past that is
needed to explain the future behavior of a circuit
Week 11: Sequential Logic Circuits

The Building Block of Memory

• Bistable element – element with two stable states; building block of memory must
be bistable
• Two cross-coupled inverters have two stable states (bistable)
• A bistable element stores one bit
• Latches and flip-flops provide inputs to control the value of the state variable.
Week 11: Sequential Logic Circuits

SR Latch
• A simple sequential circuit
• Composed of two cross-coupled NOR gates
• S-set; R-reset inputs allow for the state of the latch to be controlled

Bistable states of SR latch Truth table of SR latch Graphical symbol of SR latch

Week 11: Sequential Logic Circuits

D Latch
• A refinement of the SR latch
• The data input controls what the next state should be; the clock controls when the
state should change
• When CLK = 1, the latch is transparent; when CLK = 0, the latch is opaque.

(a) D latch schematic, (b) D-latch truth table, (c) D-latch symbol
Week 11: Sequential Logic Circuits

D Flip-Flop
• Built from two back-to-back D latches
controlled by complementary clocks.
D flip-flop schematic
• Master-Slave relationship
• When CLK = 0, the master is transparent,
the slave is opaque; when CLK = 1, the
master is opaque, the slave is transparent.

D flip-flop symbols
Week 11: Sequential Logic Circuits

Registers
• A bank of flip-flops sharing a common CLK
input.
• 𝑁-bit registers require 𝑁 flip-flops
• Key building block of most sequential
circuits

A 4-bit register: (a) schematic, (b) symbol

Week 11: Sequential Logic Circuits

Enabled Flip-Flop
• D flip-flop with an Enable input
• Provides better control: data does not have to be loaded onto the flip-flop at every
clock edge.

Enabled flip-flop: (a, b) schematics, (c) symbol

Week 11: Sequential Logic Circuits

Resettable Flip-Flop
• D flip-flop with Reset input
• Used to reset all flip-flops in a system to a known state (say, 0).
• May be synchronously resettable (resets itself on the rising edge of CLK); may be
asynchronous (resets itself when RESET = TRUE)

Synchronously resettable flip-flop: (a0 schematic, (b, c) symbols

Week 11: Sequential Logic Circuits

Synchronous Logic Design

• Every circuit element is either a register or a combinational circuit
• At least one circuit element is a register.
• All registers receive the same clock signal.
• Every cyclic path contains at least one register

Flip-flop current state and next state

Thank You!