DLD Ch5

Digital Logic Design
Mano 5 Edition
th
Ch. 5 – Synchronous
Sequential Logic
Edited by Mohammad S. Alzyout

Fall 2021/2022
Headlines
5.1 Introduction
5.2 Sequential Circuits
5.3 Storage Elements: Latches
5.4 Storage Elements: Flip‐Flops
5.5 Analysis of Clocked Sequential Circuits
5.6 Skipped
5.7 State Reduction and Assignment
5.8 Design Procedure
5.1 Introduction
Most of digital devices have the ability to send,
receive, store, retrieve, and process information
represented in a binary format.
The technology enabling and supporting these

devices is critically dependent on electronic
components that can store information, i.e.,
have memory.
Sequential circuits, act as storage elements

and have memory. They can store, retain, and
then retrieve information when needed at a later
time. Our treatment will distinguish sequential
logic from combinational logic.
A block diagram of a sequential circuit is shown
in Fig. 5.1. It consists of a combinational circuit
to which storage elements are connected to form
a feedback path.
The binary information stored in these elements

defines the sequential circuit state at that time.
The outputs in a sequential circuit are a function
not only of the inputs, but also of the present
state of the storage elements. The next state of
the storage elements is also a function of
external inputs and the present state.
There are two main types of sequential circuits:

• Synchronous sequential circuit: can be
defined from the knowledge of its signals at
discrete instants of time. [This chapter]
• Asynchronous sequential circuit: depends
upon the input signals at any instant of time
and the order in which the inputs change.
Synchronization is achieved by a timing
device called a clock (clk) generator, which
provides a clock signal having the form of a
periodic train of clock pulses. Synchronous
sequential circuits that use clock pulses are
called clocked sequential circuits.
They are called synchronous circuits because
the activity within the circuit and the resulting
updating of stored values is synchronized to the
occurrence of clock pulses.
The storage elements (memory) used in clocked
sequential circuits are called flip-flops.
A flip-flop is capable of storing one bit of
information. A sequential circuit may use many
flip-flops to store as many bits as necessary.
The block diagram of a synchronous clocked
sequential circuit is shown in Fig. 5.2. The new
value is stored (i.e., the flip-flop is updated)
when a pulse of the clock signal occurs.
Propagation delays determine the minimum
interval between clock pulses that will allow
the circuit to operate correctly. The transition
from one state to the next occurs only at
predetermined intervals by the clock pulses.
A storage element in a digital circuit can
maintain a binary state as long as power is
delivered to the circuit, until directed by an
input signal to switch states.
Storage elements that operate with signal levels

are referred to as latches; those controlled by a
clock transition are flip-flops.
• Latches are level sensitive devices.

• Flip-flops are edge-sensitive devices.
• All flip-flops are constructed from latches.
SR Latch
SR latch is a circuit with two cross-coupled
NOR gates as in Fig. 5.3, or two cross-coupled
NAND gates as in Fig. 5.4, and two inputs
labeled S for Set and R for Reset.
SR Latch
When output 𝑸 = 𝟏 and 𝑸′ = 𝟎, the latch is said
to be in the set state. When 𝑸 = 𝟎 and 𝑸′ = 𝟏, it
is in the reset state. Outputs 𝑸 and 𝑸′ are
normally the complement of each other.
SR Latch
In SR latches of NOR gates, Both inputs of the
latch remain at 0, unless the state has to be
changed.
SR latches of NAND gates operates with both

inputs normally at 1, unless the state has to be
changed.
When both inputs S and R are equal to 0 [with

NOR gates] or 1 [with NAND gates], the latch
can be in either the set or the reset state,
depending on which input was most recently a
1 [with NOR gates] or 0 [with NAND gates].
SR Latch
An SR latch with a control input (En acts as
an enable signal) is shown in Fig. 5.5. when En
returns to 0 (Disabled), the circuit remains in its
state.
D Latch (Transparent Latch)
To ensure that inputs S and R are never equal
to 1 at the same time in SR latch, D latch is
constructed, as in Fig. 5.6.
D Latch (Transparent Latch)
The output follows changes in the data input as
long as the enable input is asserted. This
situation provides a path from input D to the
output, and for this reason, the circuit is often
called a transparent latch.
Various latches are shown in Fig. 5.7.
Using Using Using

NOR NAND NAND
latch latch latch

The state of a latch or flip-flop is switched by a
change in the control input. This change is
called a trigger, and the transition it causes is
said to trigger the flip-flop.
The D latch with pulses in its control input is

essentially a flip-flop that is triggered every time
the pulse goes to the logic-1 level.
As long as the pulse input remains at this level,

any changes in the data input will change
the output and the state of the latch.
The problem with the latch is that it responds
to a change in the level of a clock pulse.
The key to the proper operation of a flip-flop is
to trigger it only during a signal transition. A
clock pulse goes through two transitions: from 0
to 1 and from 1 to 0. As in Fig. 5.8, the positive
transition is defined as the positive edge and
the negative transition as the negative edge.
A latch can be modified to form a flip-flop, by

employing two latches in a special configuration
that isolates the output of the flip-flop. Or by
triggering only during a signal transition
(from 0 to 1 or from 1 to 0) and is disabled
during the rest of the clock pulse.
Edge-Triggered D Flip-Flop
The construction of a D flip-flop with two D
latches and an inverter is shown in Fig. 5.9.
Another construction of an edge-triggered D flip-
flop uses three SR latches as in Fig. 5.10.
Negative Edge-Triggered
Positive
Edge-Triggered
Edge-Triggered D Flip-Flop
The graphic symbol for the edge-triggered D
flip-flop is shown in Fig. 5.11.
Other Flip-Flops
VLSI circuits contain several thousands of gates
within one package. D flip-flop is the most
common type, because it requires the smallest
number of gates.
Two flip-flops less widely used in the design of
digital systems are the JK and T flip-flops.
Three operations is performed with a flip-flop:
Set it to 1, reset it to 0, or complement its output.
D flip-flop can only set or reset the output, while
JK flip-flop performs all three operations.
Other Flip-Flops
The circuit diagram of a JK flip-flop constructed
with a D flip-flop and gates is in Fig. 5.12.
J sets to 1, K resets to 0, both complement it.
Other Flip-Flops
The T (toggle) flip-flop is a complementing flip-
flop and can be obtained from a JK flip-flop
when inputs J and K are tied together. Or from
D flip-flop with XOR gate. As in Fig. 5.13.
Characteristic Tables
Characteristic table defines logical properties
of a flip-flop by describing its operation in
tabular form. The characteristic tables of three
types of flip-flops are presented in Table 5.1.
Characteristic Equations
The logical properties can be expressed
algebraically with a characteristic equation.
D flip-flop →𝑸 𝒕+𝟏 =𝑫
JK flip-flop → 𝑸 𝒕 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸
T flip-flop → 𝑸 𝒕 + 𝟏 = 𝑻𝑸′ + 𝑻′ 𝑸 (𝑇 + 𝑄)
Note that the values of D, J, K, and T of the

characteristic equations in the present state
determine the next state of the flip-flop.
Direct Inputs
Some flip-flops have asynchronous inputs that
are used to force the flip-flop to a particular
state independently of the clock.
The input that sets the flip-flop to 1 is called

preset or direct set. The input that clears the
flip-flop to 0 is called clear or direct reset.
The direct inputs are useful when power is
turned on in a digital system, because the state
of the flip-flops is unknown.
A positive-edge-triggered D flip-flop with active-

low asynchronous reset is shown in Fig. 5.14
Analysis describes what a given circuit will do
under certain operating conditions. The outputs
and the next state are both a function of the
inputs and the present state.
The analysis of a sequential circuit consists of
obtaining a table or a diagram for the time
sequence of inputs, outputs, and internal states.
It is possible to write Boolean expressions that
describe the behavior of the sequential circuit,
with necessary time sequence.
A state table and state diagram describe the
behavior of the sequential circuit.
State Equations
A state equation (also called a transition
equation) specifies the next state as a function
of the present state and inputs.
Consider the sequential circuit shown in Fig.

5.15. The set of state equations for the circuit:
State Equations
The left side of the previous equations denotes
the next state of the flip-flop one clock edge
later.
The right side specifies the present state and

input conditions that make the next state
equal to 1.
Previous logic circuit acts as a 0-detector by

asserting its output (make it 1) when a 0 is
detected in a stream of 1’s.
State Equations
We can omit the designation (t) after each
variable :
The present-state value of the output can be

expressed algebraically as:
By removing the symbol (t), we get:

State Table
The time sequence of inputs, outputs, and flip-
flop states can be enumerated in a state table
(transition table). The state table for the
circuit of Fig. 5.15 is shown in Table 5.2.
The next-state section shows the states of the

flip-flops one clock cycle later, at time t + 1. The
next-state values are determined from the
logic diagram or from the state equations.
State Table
State Table
In general, a sequential circuit with m flip-flops
and n inputs needs 𝟐𝒎+𝒏 rows in the state table.
The binary numbers from 0 through 𝟐𝒎+𝒏 − 𝟏
are listed under the present-state and input
columns.
The next-state section has m columns, one for

each flip-flop. The output section has as many
columns as there are output variables. Its
binary value is derived from the circuit or from
the Boolean function in the same manner as
in a truth table.
State Table
It is sometimes convenient to express the state
table in a different form, as in Table 5.3.
State Diagram
In the state diagram, a state is represented by
a circle, and the (clock-triggered) transitions
between states are indicated by directed lines
connecting the circles.
The state diagram of Fig. 5.15 is in Fig. 5.16.

providing same information of the state table.
The binary number inside each circle identifies
the state of the flip-flops. The directed lines
are labeled with two binary numbers separated
by a slash. The input value is labeled first,
and the output is labeled after the slash.
State Diagram
State Table
Flip-Flop Input Equations
The part of the circuit that generates external
outputs is described algebraically by a set of
Boolean functions called output equations.
The part of the circuit that generates the inputs

to flip-flops is described by flip-flop input
equations (or, excitation equations).
The following input equation specifies an OR

gate with inputs x and y connected to the D
input of a flip-flop whose output is labeled
with the Q:
𝑫𝑸 = 𝒙 + 𝒚
Flip-Flop Input Equations
The sequential circuit of Fig. 5.15 consists of
two D flip-flops A and B, an input x, and an
output y.
The logic diagram of the circuit can be expressed

algebraically with two flip-flop input equations
and an output equation:
𝑫𝑨 = 𝑨𝒙 + 𝑩𝒙
𝑫𝑩 = 𝑨′ 𝒙
𝒚 = 𝑨 + 𝑩 𝒙′
Analysis with D Flip-Flops
The circuit we want to analyze is described by
the input equation:
No output equations are given, which implies

that the output is the output of the flip-flop.
The state table has one column for the present
state of flip-flop A, two columns for the two
inputs, and one column for the next state of A.
The state diagram consists of two circles, one
for each state. As shown in Fig. 5.17.
Analysis with JK Flip-Flops
For a D flip-flop, the state equation is the same
as the input equation. For JK or T flip-flops it is
necessary to refer to the characteristic table
or equation to obtain the next state values.
The procedure using the characteristic table:

1. Determine the flip-flop input equations.
2. List the binary values of each input equation.
3. Use the corresponding flip-flop characteristic
table to determine the next-state values.
An example is shown in Fig. 5.18.

The present-state and input columns of the
state table, as shown in Table 5.4, list the
eight binary combinations.
The binary values listed under the columns

labeled flip-flop inputs are not part of the
state table, but they are needed for the
purpose of evaluating the next state as specified
in step 2 of the procedure.
The next state is evaluated from the J and K

inputs and the characteristic table of the JK
flip-flop listed in Table 5.1.
The next-state values can also be obtained by
evaluating the state equations from the
characteristic equation.
This is done by using the following procedure:

1. Determine the flip-flop input equations.
2. Substitute them in the flip-flop characteristic
equation to obtain the state equations.
3. Use the state equations to determine the
next-state values in the state table.
The characteristic equations for the flip-flops
are obtained by substituting A or B for the name
of the flip-flop, instead of Q:
Substituting 𝑱𝑨 and 𝑲𝑨 from the input equations:

The state diagram of the sequential circuit is
shown in Fig. 5.19.
Analysis with T Flip-Flops
The analysis of a sequential circuit with T flip-
flops follows the same procedure outlined for
JK flip-flops.
The next-state values

in the state table can be
obtained by using either
characteristic table:
Or the characteristic equation:

Now consider the sequential circuit shown in
Fig. 5.20. It has two flip-flops A and B, one
input x, and one output y.
The state table is listed in Table 5.5. The next

state can be derived from the state equations
by substituting 𝑻𝑨 and 𝑻𝑩 in the characteristic
equations, yielding:
The next-state values for A and B in the state
table are obtained from the expressions of the
two state equations.
The state diagram of the circuit is shown in
Fig. 5.20 (b). As long as input x is equal to 1,
the circuit behaves as a binary counter with a
sequence of states 00, 01, 10, 11 & back to 00.
When x = 0, the circuit remains in the same
state. Output y is equal to 1 when the present
state is 11.
Here, the output depends on the present state
only and is independent of the input. The two
values inside each circle and separated by a
slash are for the present state and output.

DLD Ch5

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DLD Ch5

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Digital Logic Design

Edited by Mohammad S. Alzyout

The technology enabling and supporting these

Sequential circuits, act as storage elements

The binary information stored in these elements

There are two main types of sequential circuits:

Storage elements that operate with signal levels

• Latches are level sensitive devices.

SR latches of NAND gates operates with both

When both inputs S and R are equal to 0 [with

Using Using Using

latch latch latch

The D latch with pulses in its control input is

As long as the pulse input remains at this level,

A latch can be modified to form a flip-flop, by

Note that the values of D, J, K, and T of the

The input that sets the flip-flop to 1 is called

A positive-edge-triggered D flip-flop with active-

Consider the sequential circuit shown in Fig.

The right side specifies the present state and

Previous logic circuit acts as a 0-detector by

The present-state value of the output can be

By removing the symbol (t), we get:

The next-state section shows the states of the

The next-state section has m columns, one for

The state diagram of Fig. 5.15 is in Fig. 5.16.

The part of the circuit that generates the inputs

The following input equation specifies an OR

The logic diagram of the circuit can be expressed

No output equations are given, which implies

The procedure using the characteristic table:

An example is shown in Fig. 5.18.

The binary values listed under the columns

The next state is evaluated from the J and K

This is done by using the following procedure:

Substituting 𝑱𝑨 and 𝑲𝑨 from the input equations:

The next-state values

Or the characteristic equation:

The state table is listed in Table 5.5. The next

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