SEQUENTIAL CIRCUITS

- Essentially, they are combinational circuits with added memory

elements to store previous states and feedback.
- The output at any given time depends on the external inputs as well as
some stored information determined by the previous inputs.
- Memory devices in a sequential circuit that are capable of storing
binary information are called bistables or flip-flops.

TWO MAIN TYPES OF SEQUENTIAL CIRCUITS

1. SYNCHRONOUS Sequential Circuits

- These are systems whose behavior can be defined from the knowledge
of its signals at discrete instances of time.
- Clocked sequential circuits, which change state at the clock pulse
transition (therefore, a presence of master-clock generator).

2. ASYNCHRONOUS Sequential Circuits

- They depend upon the order in which its input signal changes and can
be affected at any time.
- They are faster but are more complicated and are prone to
malfunction.

NOTES012 SEQUENTIAL CIRCUITS page 1

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
BASIC FLIP-FLOP CIRCUIT: THE LATCH
- a type of memory storage device that has two stable states (bistable)
and is normally placed in a category separate from that of flip-flops.
- Latches are basically similar to flip -flops, the main difference
between them is in the method used for changing their state.
- A latch can be implemented using 2 NOR gates or 2 NAND gates.

The figure below shows a cross-coupled NOR gate implementation of an

S-R latch (also called a direct-coupled S-R flip-flop).

Note:

The figure below shows a cross-coupled NAND gate implementation

of an S-R latch.

Note:

NOTES012 SEQUENTIAL CIRCUITS page 2

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
FLIP-FLOP (F/F)
- It is a memory element or a binary cell which can store 1 bit of
information indefinitely (as long as power is delivered to the circuit)
until directed by an input signal to switch states.
- It has normally 2 outputs: Q - normal/true output and Q’ -
complementary output. That is why, a flip-flop is also called a
bistable.

FOUR FLIP-FLOP FUNCTIONS

1. Reset
2. Set
3. Toggle
4. No change

FOUR TYPES OF FLIP-FLOPS

(A) S-R (Set-Reset) Flip-Flop
(B) D (Data or gated D-latch) Flip-Flop
(C) J-K Flip-Flop
(D) T (Toggle) Flip-Flop

(A) S-R FLIP-FLOP

The S-R latch can be modified into an S-R flip-flop by providing an
additional control input that determines when the state of the circuit is to be
changed. Usually, this additional control is in the form of a clock pulse
(CP).

Logic diagram and characteristic table of SR F/F

NOTES012 SEQUENTIAL CIRCUITS page 3
SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Schematic symbol:

Characteristic equation derived from the characteristic table of SR F/F:

(B) D Flip-Flop
One way to eliminate the undesirable condition of the indeterminate
state in the S-R flip-flop is to ensure that inputs S and R are never equal to 1
at the same time. This is done in the D flip-flop. The D flip-flop receives the
designation from its ability to hold data into its internal storage.

Logic diagram and characteristic table of D F/F

Schematic symbol:

Characteristic equation derived from the characteristic table of D F/F:

NOTES012 SEQUENTIAL CIRCUITS page 4

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
(C) J-K Flip-Flop
A J-K flip-flop is a refinement of the S-R flip-flop in that the
indeterminate state of the S-R flip-flop is defined in the J-K flip-flop. Inputs
J and K behave like S and R, to set and reset the flip-flop, respectively.
J S (set) and K R (reset).

Logic diagram and characteristic table of JK F/F

Schematic symbol:

Characteristic equation derived from the characteristic table of JK F/F:

(D) T Flip-Flop
The T flip-flop is a single -input version of the J-K flip-flop. The
designation T comes from the ability of the flip-flop to “toggle” or
complement its state.

NOTES012 SEQUENTIAL CIRCUITS page 5

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
 Logic diagram and characteristic table of T F/F

Schematic symbol:

Characteristic equation derived from the characteristic table of T F/F:

TRIGGERING OF FLIP-FLOPS
Triggering is referred to as the momentary change at the input that
switches state of a flip-flop.
Triggering events includes:
Triggering transactions can be any of the following:

Two Modes of Triggering:

1. Level Triggering – flip-flop changes state during pulse duration.
a) Positive-Level Triggering – would accept input at logic 1 of clock pulse.
b) Negative-Level Triggering – would accept input at logic 0 of clock pulse.
2. Edge Triggering – flip-flop is sensitive to pulse transition rather than
pulse duration.
a) Positive-Edge Triggering – would accept input at positive-going edge.
b) Negative-Edge Triggering – would accept input at negative-going edge.

NOTES012 SEQUENTIAL CIRCUITS page 6

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Example 1. Given the waveforms for the D input and the clock, determine
the Q output waveform in the flip-flop starts out RESET. Assume that the
positive edge-triggered flip-flop is given.

Example 2. The waveforms are applied to the J, K and clock inputs as

indicated. Determine the Q output, assuming that the negative edge-triggered
flip-flop is initially RESET.

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
ASYNCHRONOUS PRESET AND CLEAR INPUTS OF F/F

The flip-flops discussed in the previous section are called

synchronous inputs because data on these inputs are transferred to the flip-
flop’s output only on the triggering edge of the clock pulse; that is, the data
are transferred synchronously with the clock. Most integrated circuit flip-
flops also have asynchronous inputs. These are inputs that affect the state
of the flip-flop independent of the clock. The two most common
asynchronous inputs are:
• preset (PRE) or direct set (SD) will set the flip-flop
• clear (CLR) or direct reset (RD) will reset the flip-flop
• These are usually active-LOW inputs, as indicated by the bubbles.
• These preset and clear inputs must both be kept HIGH for synchronous
operation.

Example:
For the positive edge-triggered J-K flip-flop with preset and clear
inputs, determine the Q output for the inputs shown in the timing diagram if
Q is initially LOW.

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
MASTER-SLAVE FLIP-FLOP

Another class of flip-flop is the pulse -triggered master-slave, which

has largely been replaced by edge-triggered devices. Data are entered into
the flip-flop at the leading edge of the clock pulses, but the output does not
reflect the input state until the trailing edge. The pulse-triggered master-
slave flip-flop does not allow data to change while the clock pulse is active.

Logic diagram of master-slave SR F/F

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

Steps:
1. Identify the circuit parameters: # of F/F, F/F type, external inputs and
outputs.
2. Express the F/F inputs as a function of any external input and/or present
state. Express external outputs (if present) as a function of external inputs
and/or present states.
3. Obtain the next state equation [Q(t+1)] of each F/F as a function of
present states and/or inputs.
4. Construct a transition table. It consists of present state, F/F inputs,
external input, next state and external output.

5. Construct a state table. It enumerates the time sequence of inputs, outputs

and F/F states. State table is consists of four sections: present state, external
input, next state and output. Present state section shows state of F/F at any
given time t, Q(t). Input section gives the value of external input for each
possible present state. Next state section shows state of F/F one clock period
later, Q(t+1) . Output section gives the value of external output for each
present state.
6. Draw the corresponding state diagram. State diagram is a graphical
representation of information in the state table. A circle represents a state in
the sequential circuit, and directed lines connecting the circles indicate the
transition between states. The binary number inside each circle identifies
the state of the flip-flops in the sequential circuit. The directed lines are
labeled with two numbers separated by a slash, which are input value/output
value during the present state.
7. Apply state reduction if possible. State reduction is concerned with
procedure for reducing the number of states in a state table while keeping the
external input/output requirements unchanged. The objective of which is to
reduce the number of flip-flops in a sequential circuit.

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Example 1.
For the sequential circuit illustrated below, obtain the following:
(a) F/F input and external output equations
(b) F/F next state equations
(c) Transition and state table
(d) State diagram

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Solution:

1. Generalization:
• There are two (2) D flip-flops DA and DB
• One external input X
• One external output Y

2. F/F inputs and external output as functions of any external input and/or
present states.

3. Next-state equations:
• The next state equation (characteristic equation) for a D flip-flop is
D = Q(t+1) . Therefore, the next-state equations for D flip-flops A and B are:

4. # of transition table combinations: 8

PRESENT EXTERNAL F/F NEXT STATE EXTERNAL

STATE INPUT INPUT OUTPUT
QA(t) QB(t) X DA DB QA(t+1) QB(t+1) Y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0
NOTES012 SEQUENTIAL CIRCUITS page 12
SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
5. Two-dimensional state table: present state is tabulated in the left column
and inputs are tabulated across the top rows.
PRESENT NEXT STATE EXTERNAL
STATE OUTPUT
X=0 X=1 X=0 X=1
QA(t) QB(t) QA(t+1) QB(t+1) QA(t+1) QB(t+1) Y Y
00 00 01 0 0
01 00 11 1 0
10 00 10 1 0
11 00 10 1 0

• 2 n F/F = # of state of the sequential circuit

• 22 = 4 states

One-dimensional state table: present state is tabulated in the left column

and external input is tabulated on the next column.
PRESENT EXTERNAL NEXT STATE EXTERNAL
STATE INPUT OUTPUT
QA(t) QB(t) X QA(t+1) QB(t+1) Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

6. State diagram:

NOTES012 SEQUENTIAL CIRCUITS page 13

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
7. State Reduction:

• Two states are said to be equivalent (therefore considered as

redundant) if and only if for each member of the set of inputs, they
give exactly the same output and send the circuit either to the same
state or to an equivalent state.
• For the two dimensional state table, let state 00 = a, state 01 = b, state
10 = c and state 11 = d.
PRESENT NEXT STATE EXTERNAL
STATE OUTPUT
X=0 X=1 X=0 X=1
QA(t) QB(t) QA(t+1) QB(t+1) QA(t+1) QB(t+1) Y Y
a a b 0 0
b a d 1 0
c a c 1 0
d a c 1 0

NOTES012 SEQUENTIAL CIRCUITS page 14

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Having simplified the state table, the state diagram is redrawn as

NOTES012 SEQUENTIAL CIRCUITS page 15

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Example 2.
For the sequential circuit illustrated below, obtain the following:
(a) F/F input and external output equations
(b) F/F next state equations
(c) Transition and state table
(d) State diagram

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Solution:
1. Generalization:
• There are two J-K flip-flops (A & B)
• One external input X
• No external outputs

2. F/F inputs and external output as functions of any external input and/or
present states.

3. Next-state equations:
• Τhe next state equation (characteristic equation) for the J-K flip-flops
are as follows:

4. # of transition table combinations: 8

NOTES012 SEQUENTIAL CIRCUITS page 17

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
5. Two dimensional state table:

6. State Diagram:

7. State Reduction:

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Redraw the state diagram:

DESIGN OF CLOCKED SEQUENTIAL CIRCUITS

Steps:
1. Obtain either the state diagram or state table from the statement of the
problem.
2. If only a state diagram is available form step 1, obtain the state table.
3. Apply state reduction if possible.
4. Create the state table of the reduced state diagram.
5. Choose the F/F type. Determine the number of flip-flops to be used.
• 2 n F/F > # of state of the sequential circuit
6. Create the transition table and F/F excitation table.

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
7. Derive the simplified F/F input equations and external output equations.
8. Draw the logic diagram of the sequential circuit.

Example 1. Design the sequential circuit for the given state diagram using
J-K F/Fs. The sequential circuit has one input (X) and one output (Z).

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
Solution:
1. From the state diagram given, the state table is obtained. State 101,
110 and 111 are considered as don’t care states.

2. Apply state reduction if possible: NO REDUNDANT STATES!

3. Transition table and excitation table

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SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo
4. Simplified flip-flop input functions and output equations using K-map:

5. Logic diagram:

NOTES012 SEQUENTIAL CIRCUITS page 22

SWIDLEC LECTURE NOTES by Engr. Analene Montesines-Nagayo