Sarala T

Asst. Prof.
E&CE Dept.
SVCE, BEngaluru

DE Module 3 NOTES
Module 3: Flip Flops
Combinational Circuits:
 Logic circuits for digital systems may be combinational or sequential.
 A combinational circuit consists of input variables, logic gates, and output variables.
 The circuit in which outputs depends on only present value of inputs. So it is possible to describe
each output as function of inputs by using Boolean expression. No memory element involved.
No clock input. Circuit is implemented by using logic gates. The propagation delay depends on,
delay of logic gates. Examples of combinational logic circuits are : full adder, subtractor,
decoder, code converter, multiplexers

Sequential Circuits:



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Every digital system is likely to have combinational circuits, most systems encountered in
practice also include storage elements, which require that the system be described in term of
sequential logic.
A sequential circuit may use many flip-flops to store as many bits as necessary. The outputs
can come either from the combinational circuit or from the flip-flops or both.
 Sequential Circuit is the logic circuit in which output depends on present value of inputs at that
instant and past history of circuit i.e. previous output. The past output is stored by using memory
device. The internal data stored in circuit is called as state.
 The clock is required for synchronization. The delay depends on propagation delay of circuit and
clock frequency. The examples are flip-flops, registers, counters etc.
Latches and Flip-Flops:
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store
one bit of information. The main difference between latches and flip-flops is that for latches, their
outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words,
when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the
other hand, have their content change only either at the rising or falling edge of the enable signal. This
enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the
flip-flop content remains constant even if the input changes.

There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major
differences in these flip-flop types are the number of inputs they have and how they change state. For
each type, there are also different variations that enhance their operations. In this chapter, we will look
at the operations of the various latches and flip-flops.

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Difference between Latches & Flip flops:
Basic Bi-stable elements:
 The simplest sequential circuit or storage element is a bistable element, which is constructed
with two inverters connected sequentially in a loop as shown in Figure 1.
 It has no inputs and two outputs labeled Q and Q`. Since the circuit has no inputs, we cannot
change the values of Q and Q`
 Using the signal Q as the state variable to describe the state of the circuit, we can say that the
circuit has two stable states: Q = 0, and Q = 1; hence the name “bistable.”

Analog Analysis of Bistable element:

An analog analysis of a bistable element, however, reveals that it has three equilibrium points and
not two as found from the digital analysis. Assuming again that Q = 1, and we plot the output voltage

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(Vout1) versus the input voltage (Vin1) of the top inverter, we get the solid line in Figure 2. The dotted
line shows the operation of the bottom inverter where Vout2 and Vin2 are the output and input voltages
respectively for that inverter.
Figure 2 shows that there are three intersection points, two of which corresponds to the two stable
states of the circuit where Q is either 0 or 1. The third intersection point labeled metastable, is at a
voltage that is neither a logical 1 nor a logical 0 voltage. Nevertheless, if we can get the circuit to
operate at this voltage, then it can stay at that point indefinitely. Practically, however, we can never
operate a circuit at precisely a certain voltage. A slight deviation from the metastable point as cause by
noise in the circuit or other stimulants will cause the circuit to go to one of the two stable points. Once
at the stable point, a slight deviation, however, will not cause the circuit to go away from the stable
point but rather back towards the stable point because of the feedback effect of the circuit.
An analogy of the metastable behavior is a ball on top of a symmetrical hill as depicted in Figure 3.
The ball can stay indefinitely in that precarious position as long as there is absolutely no movement
whatsoever. With any slight force, the ball will roll down to either of the two sides. Once at the bottom
of the hill, the ball will stay there until an external force is applied to it. The strength of this external
force will cause the ball to do one of three things. If a small force is applied to the ball, it will go partly
up the hill and then rolls back down to the same side. If a big enough force is applied to it, it will go
over the top and down the other side of the hill. We can also apply a force that is just strong enough to
push the ball to the top of the hill. Again at this precarious position, it can roll down either side.
 We will find that all latches and flip-flops have this metastable behavior. In order for the element
to change state, we need to apply a strong enough pulse satisfying a given minimum width requirement.
Otherwise, the element will either remain at the current state or go into the metastable state in which
case unpredictable results can occur.
SR Latch:
The bistable element is able to remember or store one bit of information. However, because it does
not have any inputs, we cannot change the information bit that is stored in it. In order to change the
information bit, we need to add inputs to the circuit. The simplest way to add inputs is to replace the
two inverters with two NAND gates as shown in Figure.
This circuit is called a SR latch. In addition to the two outputs Q and Q', there are two inputs S' and

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R' for set and reset respectively. Following the convention, the prime in S and R denotes that these
inputs are active low. The SR latch can be in one of two states: a set state when Q = 1, or a reset state
when Q = 0.
NOR Gate S R latch:
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 Timing Diagram for NOR gate SR latch

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SR Latch using NAND gate:

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 Timing Diagram for NAND Gate SR latch
Gated S R Latch:
The operation of the basic SR latch can be modified by providing an additional control input that
determines when the state of the latch can be changed. In Fig. 5-5, it consists of the basic SR latch and
two additional NAND gates.

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Applications of SR Latch
 SR Flip flop is used in the Digital Logic circuit for the switch or the circuit breaker to hold the
closed state even the input controlling signal disappears.
 As a Digital latching relay it can be used.
 As a switching mechanism for alarm circuit, which is when an alarm is pressed it will not get
reset until the reset button is pressed.

D latch:
One way to eliminate the undesirable condition of the indeterminate state in SR latch is to ensure that
inputs S and R are never equal to 1 at the same time in Fig 5-5. This is done in the D latch.

Gated D latch:
Just like the SR latch with an enable input, the D latch can also have an enable input as shown in fig.

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When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the latch is said
to be “open” and the path from the input D to the output Q is “transparent”. Hence the circuit is often
referred to as a transparent latch. When E is de-asserted (E = 0), the latch is disabled or “closed”, and
the Q output retains its last value independent of the D input. A sample timing diagram for the operation
of the D latch with enable is shown in Figure 9(d). Between t0 and t1, the latch is enabled with E = 1
so the output Q follows the input D. Between t1 and t2, the latch is disabled, so Q remains stable even
when D changes.
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Graphic Symbols for latches

A latch is designated by a rectangular block with inputs on the left and outputs on the right. One output
designates the normal output, and the other designates the complement output.
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Flip flops:
The state of a latch or flip-flop is switched by a change in the control input. This momentary change is
called a trigger and the transition it cause is said to trigger the flip-flop. The D latch with pulses in its
control input is essentially a flip-flop that is triggered every time the pulse goes to the logic 1 level. As
long as the pulse input remains in the level, any changes in the data input will change the output and the
state of the latch.
SR Flip Flops:

Truth table of SR Flip-Flop:

CLK State INPUT OUTPUT

Clock S R Q Q’

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HIGH
HIGH
x
0
1
x
0
0
0
0
1
1
1
0
HIGH 0 1 0 1
HIGH 1 1 1 0
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D-type Flip-Flop Circuit

The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures that
inputs S and R are never equal to one at the same time. The D-type flip flop are constructed from a
gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D
(data) input.

Then this single data input, labelled “D” and is used in place of the “Set” signal, and the inverter is
used to generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop
from a level-sensitive SR-latch as now S = D and R = not D as shown.
We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and one to
“RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and
“RESET” the flip-flop using just one input as now the two input signals are complements of each other.
This complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since that
state is no longer possible.

Thus this single input is called the “DATA” input. If this data input is held HIGH the flip flop would
be “SET” and when it is LOW the flip flop would change and become “RESET”. However, this would
be rather pointless since the output of the flip flop would always change on every pulse applied to this
data input.

To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data
input from the flip flop’s latching circuitry after the desired data has been stored. The effect is that D
input condition is only copied to the output Q when the clock input is active. This then forms the basis
of another sequential device called a D Flip Flop.

The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the
clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are
both held at logic level “1” so it will not change state and store whatever data was present on its output
before the clock transition occurred. In other words the output is “latched” at either logic “0” or logic
“1”.

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Edge triggered D Flip Flop:
Truth Table for the D-type Flip Flop

Clk D Q Q Description
Memory
↓»0 X Q Q
no change
↑»1 0 0 1 Reset Q » 0

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↑»1 1 1 0 Set Q » 1

Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are edge
triggered.

Timing diagram for Edge triggered D flip flop:

Applications of D flip flop

 The Edge triggered D flip flops are used in the sampling circuits to sample the date at
particular time interval. i.e. at a sharp interval when the clock changes from low to high the
input data will be delivered to the output and it remains the same until the next clock low to
high. We can adjust the sampling intervals by changing the clock pulse widths.
 It is used as a buffer to store the intermediate data.
 It is also used to introduce the delay in the circuits.

JK flip flop:

JK Flip flop is the ideal and important memory element which behaves the same fashion as RS flip flop
except the condition where R & S equals to 1. It is a forbidden in RS flip flop, the JK flip flop is an
improved version which avoids this prohibited or impracticable state and converts in to toggle state.
i.e. when J=1 and K=1 the output is the inversion of the last state. J and K in the JK flip flop means
Jack and Kilby who invented this flip flop combination. This toggling condition is mostly used in the
counters.

Clk J K Qt+1 Action

H 0 0 Q Latched ( No change)
H 0 1 0 Reset

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H 1 0 1 Set
H Q(ba
1 1 Toggle
r)

Figure shows the circuit diagram of JK flip flop in which two AND gates are placed input to the SR
flip flop. One input of AND gate is J or K and second input is the feedback parameter of output, in a
summarized way the inputs of first AND gate is J &~Q (Q bar) and the second gate inputs are R & Q.
A clock signal is provide to the both AND gates for enabling or disabling the flip flop operation. The
following points shows the operating conditions of JK flip flop:

 When J & K are low(i.e. 0), the two AND gates will disable irrespective of the Q & ~Q and two
inputs to S&R FF will be zero which gives a no state condition. This condition is called latched
condition as the flip flop retains its last value.
 When J is Low and K is High the upper or first AND gate disables, therefore there is no way to
set the output of flip flop only the flip flop will be reset if the lower AND is high (i.e. 1). i.e.
when the second input of lower AND gate Q is high then the output becomes High which sends
a reset signal to SR flip flop and resets the flip flop (Q changes from 1–>0). Once FF resets Q
becomes 0 and lower AND also disables and leads to no change condition of flip flop even the
clock pulse is high.
 When J is High & K is Low, the lower AND gate gets disables which disables the resetting
condition of flip flop. So the flip flop can only be set if the upper AND gate is enable. When a
Q is low ~Q will be high, this drives the upper AND gate to high with J is already high. The
high output of upper AND gate drives the S input of SR flip flop which sets the flip flop output
 to high (Q=1). After this again the two AND gates are disabled because of ~Q=0 in this
condition and it leads to no change condition.
 When J & K is High both AND gates can be enabled which is possible to SET or RESETS the
flip flop. It is very important condition as it toggles the flip flop output states. Suppose if Q is
high (FF last state) then lower AND gate enables which sends a reset signal to the flip flop and
the output becomes Low. If Q is low ~Q will be high thus enables the upper AND gate which
delivers a set signal to the flip flop and the output becomes High. This is illustrated as the clock
is enabled and inputs J&K high the flip flop will be toggling mode and complements its output
from its last output.

Race around condition of JK Flip Flop

In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or
complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing
or racing condition. Consider above J&K circuit diagram as long as clock is high and J&K=11 then
two upper and lower AND gates are only triggered by the complementary outputs Q and Q(bar). I.e. in
any condition according to the propagation delay one gate will be enabled and another gate is disabled.
If upper gate is disabled then it sets the output and in the next lower gate will be enabled which resets
the flip flop output.

Steps to avoid racing condition in JK Flip flop:

 If the Clock On or High time is less than the propagation delay of the flip flop then racing can
be avoided. This is done by using edge triggering rather than level triggering.
 If the flip flop is made to toggle over one clock period then racing can be avoided. This

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introduced the concept of Master Slave JK flip flop.

The T Flip-Flop

The essential characteristic of a flip-flop is that it changes its output state in response to a positive or
negative transition on the control signal. But there is more to a flip-flop than this: we also have to define
the input-to-output relationship. This is why there are different types of flip-flops; they are all sensitive
to clock edges, but they perform different actions in response to the input states.

The “T” in “T flip-flop” stands for “toggle.” When you toggle a light switch, you are changing from
one state (on or off) to the other state (off or on). This is equivalent to what happens when you provide
a logic-high input to a T flip-flop: if the output is currently logic high, it changes to logic low; if it’s
currently logic low, it changes to logic high. A logic-low input causes the T flip-flop to maintain its
current output state.

Here is the same information in truth-table form:

From SR or JK to T

You can modify the input-to-output relationship of an existing flip-flop by adding logic gates and
appropriate interconnections. AAC already has an abundance of information on this topic; if you want
to explore the details, our article on the conversion of flip-flops is a good place to start. In this short
article, I’ll simply present two ways to create a T flip-flop from an existing flip-flop.

If you have an SR flip-flop, all you need is two AND gates to turn it into a T flip-flop:

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The process is even easier if you’re starting with a JK flip-flop. No additional gates are required; all
you need to do is connect the same input signal to both input pins:

T flip-flops are handy when you need to reduce the frequency of a clock signal: If you keep the T input
at logic high and use the original clock signal as the flip-flop clock, the output will change state once
per clock period (assuming that the flip-flop is not sensitive to both clock edges). Thus, the output clock
will be half the frequency of the input clock.

Master Slave Flip Flop:

Master Slave flip flop are the cascaded combination of two flip-flops among which the first is
designated as master flip-flop while the next is called slave flip-flop (Figure 1). Here the master flip-
flop is triggered by the external clock pulse train while the slave is activated at its inversion i.e. if the
master is positive edge-triggered, then the slave is negative-edge triggered and vice-versa. This means
that the data enters into the flip-flop at leading/trailing edge of the clock pulse while it is obtained at
the output pins during trailing/leading edge of the clock pulse. Hence a master-slave flip-flop completes
its operation only after the appearance of one full clock pulse for which they are also known as pulse-
triggered flip-flops.
Master Slave J K flip flops:

The internal structure of a master-slave JK flip-flop in terms of NAND gates and an inverter (to
complement the clock signal) is shown in Figure 2. Here it is seen that the NAND gate 1 (N1) has three
inputs viz., external clock pulse (Clock), input J and output Q̅; while the NAND gate 2 (N2) has external
clock pulse (Clock), input K and output Q as its inputs.

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Further the outputs of N1 and N2 gates are connected as the inputs for the crisscross connected gates
N3 and N4. These four gates together (N1, N2, N3 and N4) form the master-part of the flip-flop while
a similar arrangement of the other four gates N5, N6, N7 and N8 form the slave-part of it.

From figure it is also evident that the slave is driven by the outputs of the master (M1 and M2), which
is in accordance with its name master-slave flip-flop. Further the master is active during the positive
edge of the clock due to which M1 and M2 change their states; depending on the values of J and K.
However at this instant the outputs of the overall system (master-slave JK flip-flop) remains unchanged
as the slave will be inactive due to positive-edge of the clock pulse. Similar to this, the slave decides
on its outputs Q and Q̅ depending on its inputs M1 and M2, during the negative edge of the clock during
which the master will be inactive.

The truth table corresponding to the working of the flip-flop shown in Figure 2 is given by Table I.
Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in red boxes) appear

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during the positive-edge of the clock (red arrow). However at this instant the slave-outputs remain
latched or unchanged. The same data is transferred to the output pins of the master-slave flip-flop (data
enclosed in blue boxes) by the slave during the negative edge of the clock pulse (blue arrow). The same
principle is further emphasized in the timing diagram of master-slave flip-flop shown by Figure 3. Here
the green arrows are used to indicate that the slave-output is nothing but the master-output delayed by
half-a-clock cycle. Moreover it is to be noted that the working of any other type of master-slave flip-
flop is analogous to that of the master slave JK flip-flop explained here.
The Master-Slave D Flip Flop

The basic D-type flip flop can be improved further by adding a second SR flip-flop to its output that
is activated on the complementary clock signal to produce a “Master-Slave D-type flip flop”. On the
leading edge of the clock signal (LOW-to-HIGH) the first stage, the “master” latches the input
condition at D, while the output stage is deactivated.

On the trailing edge of the clock signal (HIGH-to-LOW) the second “slave” stage is now activated,
latching on to the output from the first master circuit. Then the output stage appears to be triggered on
the negative edge of the clock pulse. “Master-Slave D-type flip flops” can be constructed by the
cascading together of two latches with opposite clock phases as shown.

The Master-Slave D Flip Flop Circuit

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We can see from above that on the leading edge of the clock pulse the master flip-flop will be loading
data from the data D input, therefore the master is “ON”. With the trailing edge of the clock pulse the
slave flip-flop is loading data, i.e. the slave is “ON”. Then there will always be one flip-flop “ON” and
the other “OFF” but never both the master and slave “ON” at the same time. Therefore, the output Q
acquires the value of D, only when one complete pulse, ie, 0-1-0 is applied to the clock input.

Master Slave SR Flip Flop

The type of SR flip-flop described here is a master-slave SR flip-flop. It is built from two gated SR
latches: one a master, and the other a slave. The master takes the flip-flops inputs: S (set), R (reset),
and C (clock). The clock input is fed to the latch's gate input. The slave takes the master's outputs as
inputs (Q to S and Qn to R), and the complement of the flip-flop's clock input. The slave's outputs are
the flip-flop's outputs. This difference in clock inputs between the two latches disconnects them and
eliminates the transparency between the flip-flop's inputs and outputs.

The schematic below shows a master-slave SR flip-flop. The two inputs S and R are used to set and
reset the data respectively. The clock input C is used to control both the master and slave latches
making sure only one of the latches can set its data at any given time. When C has the value 1, the
master latch can set its data and the slave latch cannot. When C has the value 0, the slave can set its
data and the master cannot. From this description we see that the flip-flop is level-triggered. The
outputs Q and Qn are the flip-flop's stored data and the complement of the flip-flop's stored data
respectively.

VTUPulse.com Master Slave S R Flip Flop Circuit diagram

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