UNIT – III

1. HALF ADDER

 An adder is a digital circuit that performs addition of numbers.

 The half adder adds two binary digits called as augend and addend and produces two
outputs as sum and carry; XOR is applied to both inputs to produce sum and AND
gate is applied to both inputs to produce carry.

2. FULL ADDER

 The full adder adds 3 one bit numbers, where two can be referred to as operands and
one can be referred to as bit carried in. And produces 2-bit output, and these can be
referred to as output carry and sum.
 3. HALF SUBTRACTOR

A half subtractor is a logical circuit that performs a subtraction operation on two binary
digits. The half subtractor produces a sum and a borrow bit for the next stage. As like
addition operation of 2 binary digits, which produces SUM and CARRY, the subtraction of 2
binary digits also produces two outputs which are termed as difference and borrow.

Half Subtractor Block Diagram

Half subtractor circuit diagram :

Half subtractor truth table :

D = (X’Y + XY’) = X ⊕ Y

B = X’Y

4. FULL SUBTRACTOR

Full Subtractor Block Diagram

Then the combinational circuit of a “full subtractor” performs the operation of subtraction on
three binary bits producing outputs for the difference D and borrow B-out. Just like the binary
adder circuit, the full subtractor can also be thought of as two half subtractors connected
together, with the first half subtractor passing its borrow to the second half subtractor as
follows.
As the full subtractor circuit above represents two half subtractors cascaded together, the
truth table for the full subtractor will have eight different input combinations as there are
three input variables, the data bits and the Borrow-in, BIN input. Also includes the difference
output, D and the Borrow-out.

Full Subtractor Circuit Diagram

The full subtractor boolean expressions are :
DIFF= (X’Y’Z + X’YZ’ + XY’Z’ + XYZ) = X ⊕ Y ⊕ Z
BORROW=(X’Y’Z + X’YZ’ + X’YZ + XYZ) = X'(Y ⊕ Z) + YZ

5. MULTIPLEXER

Multiplexer is a special type of combinational circuit. There are n-data inputs, one
output and m select inputs with 2m = n. It is a digital circuit which selects one of the n
data inputs and routes it to the output. The selection of one of the n inputs is done by
the selected inputs. Depending on the digital code applied at the selected inputs, one
out of n data sources is selected and transmitted to the single output Y. E is called the
strobe or enable input which is useful for the cascading. It is generally an active low
terminal that means it will perform the required operation when it is low.
A Multiplexers (MUX) is a combinational logic component that has several inputs
and only one output. MUX directs one of the inputs to its output line by using a
control bit word (selection line) to its select lines. Multiplexer contains the
followings: o data inputs o selection inputs o a single output o Selection input
determines the input that should be connected to the output. The multiplexer
sometime is called data selector.
The circuit has two data input lines, one output line and one selection line, S.
When S= 0, the upper AND gate is enabled and I0 has a path to the output. When
S=1, the lower AND gate is enabled and I1 has a path to the output.

UNIT - IV

1. RS FLIP FLOP

The SR flip-flop, also known as a SR Latch, can be considered as one of the most
basic sequential logic circuit possible. This simple flip-flop is basically a one-bit
memory bistable device that has two inputs, one which will “SET” the device
(meaning the output = “1”), and is labelled S and one which will “RESET” the
device (meaning the output = “0”), labelled R.
 Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop
back to its original state with an output Q that will be either at a logic level “1” or
logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its
outputs back to its opposing inputs and is commonly used in memory circuits to
store a single data bit. Then the SR flip-flop actually has three
inputs, Set, Reset and its current output Q relating to it’s current state or history.
The term “Flip-flop” relates to the actual operation of the device, as it can be
“flipped” into one logic Set state or “flopped” back into the opposing logic Reset
state.
The NAND Gate SR Flip-Flop
The simplest way to make any basic single bit set-reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-
Reset Bistable also known as an active LOW SR NAND Gate Latch, so that there
is feedback from each output to one of the other NAND gate inputs. This device
consists of two inputs, one called the Set, S and the other called the Reset, R with
two corresponding outputs Q and its inverse or complement Q (not-Q) as shown
below.
The Basic SR Flip-flop

2. Clocked RS FLIP FLOP

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop

that only changes state when certain conditions are met regardless of the condition
of either the Set or the Reset inputs. By connecting a 2-input AND gate in series
with each input terminal of the SR Flip-flop a Gated SR Flip-flop can be created.
This extra conditional input is called an “Enable” input and is given the prefix of
“EN“. The addition of this input means that the output at Q only changes state
when it is HIGH and can therefore be used as a clock (CLK) input making it level-
sensitive as shown below.
 Gated SR Flip-flop

When the Enable input “EN” is at logic level “0”, the outputs of the
two AND gates are also at logic level “0”, (AND Gate principles) regardless of
the condition of the two inputs S and R, latching the two outputs Q and Q into
their last known state. When the enable input “EN” changes to logic level “1” the
circuit responds as a normal SR bistable flip-flop with the two AND gates
becoming transparent to the Set and Reset signals.This additional enable input can
also be connected to a clock timing signal (CLK) adding clock synchronisation to
the flip-flop creating what is sometimes called a “Clocked SR Flip-flop“. So
a Gated Bistable SR Flip-flop operates as a standard bistable latch but the
outputs are only activated when a logic “1” is applied to its EN input and
deactivated by a logic “0”.In the next tutorial about Sequential Logic Circuits,
we will look at another type of simple edge-triggered flip-flop which is very
similar to the RS flip-flop .

3. T – Flip Flop
The name T flip-flop is termed from the nature of toggling operation. The
major applications of T flip-flop are counters and control circuits. Whenever
the clock signal is LOW, the input is never going to affect the output state.
The clock has to be high for the inputs to get active. Thus, T flip-flop is a
controlled Bi-stable latch where the clock signal is the control signal. The T flip
flop is the modified form of JK flip flop. The Q and Q’ represents the output states
of the flip-flop. According to the table, based on the input the output changes its
state. But, the important thing to consider is all these can occur only in the
presence of the clock signal. This only has the toggling function. T flip – flop is
also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state
in SR flip – flop, we should provide only one input to the flip – flop called Trigger
input or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling
means ‘Changing the next state output to complement of the present state output’.

4. D – Flip Flop
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is
that the indeterminate input condition of SET = “0” and RESET = “0” is
forbidden.
This state will force both outputs to be at logic “1”, over-riding the feedback
latching action and whichever input goes to logic level “1” first will lose control,
while the other input still at logic “0” controls the resulting state of the latch.
 But in order to prevent this from happening an inverter can be connected between
the “SET” and the “RESET” inputs to produce another type of flip flop circuit
known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just
simply a D Flip Flop as it is more generally called.
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures
that ensures that inputs S and R are never equal to one at the same time. The D-
type flip flop are constructed from a gated SR flip-flop with an inverter added
between the S and the R inputs to allow for a single D (Data) input.
Then this single data input, labelled “D” and is used in place of the “Set” signal,
and the inverter is used to generate the complementary “Reset” input thereby
making a level-sensitive D-type flip-flop from a level-sensitive SR-latch as now S
= D and R = not D as shown.

D-type Flip-Flop Circuit

 
We remember that a simple SR flip-flop requires two inputs, one to “SET” the output
and one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-
flop we can “SET” and “RESET” the flip-flop using just one input as now the two
input signals are complements of each other. This complement avoids the ambiguity
inherent in the SR latch when both inputs are LOW, since that state is no longer
possible.
Thus this single input is called the “DATA” input. If this data input is held HIGH the
flip flop would be “SET” and when it is LOW the flip flop would change and become
“RESET”. However, this would be rather pointless since the output of the flip flop
would always change on every pulse applied to this data input
5. JK Flip Flop

The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.

 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided

 2. if Set or Reset change state while the enable (EN) input is high the correct latching
action may not occur
Then to overcome these two fundamental design problems with the SR flip-flop design,
the JK flip Flop was developed.

This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered
to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened
abbreviated letters of other words, such as “S” for Set and “R” for Reset, but are themselves
autonomous letters chosen by its inventor Jack Kilby to distinguish the flip-flop design from
other types.

The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-
flop with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop”
has no invalid or forbidden input states of the SR Latch even when S and R are both at logic
“1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry
that prevents the illegal or invalid output condition that can occur when both inputs S and R
are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for
a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except
for the addition of a clock input.

The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.

The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This
cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R =
“1” state to be used to produce a “toggle action” as the two inputs are now interlocked.

If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q are always different we can use them to
 control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles as
shown in the following truth table.

UNIT – V

1. Shift Register
A group of flip-flop is known as a Register. The n-bit register will consist of
n number of flip-flop and it is capable of storing an n-bit word. The binary data in
a register can be moved within the register from one flip-flop to another. The registers that
allow such data transfers are called as shift registers.

A bit is input on the right, all the bits move one place to the left, and the leftmost bit
disappears. Shift registers are commonly used in converters that translate parallel data to
serial data, or vice-versa. Shift registers can also function as delay circuits and digital pulse
extenders.

Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop
becomes the input of the next flip-flop

 A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop

for each data bit.

 The output from each flip-Flop is connected to the D input of the flip-flop at its
right.

 Shift registers hold the data in their memory which is moved or “shifted” to their
required positions on each clock pulse.

 Each clock pulse shifts the contents of the register one bit position to either the left
or the right.

2. Difference between synchronous and Asynchronous Counter

1.In synchronous counter, all flip flops are triggered with same clock simultaneously. In
asynchronous counter, different flip flops are triggered with different clock,

2.Synchronous Counter is faster than asynchronous counter in operation. Asynchronous

Counter is slower than synchronous counter in operation.

3.Synchronous Counter does not produce any decoding errors. Asynchronous Counter
produces decoding error.
4.Synchronous Counter is also called Parallel Counter. Asynchronous Counter is also called
Serial Counter.

5.Synchronous Counter designing as well implementation are complex due to increasing the
number of states. Asynchronous Counter designing as well as implementation is very easy.

6.Synchronous Counter will operate in any desired count sequence. Asynchronous Counter
will operate only in fixed count sequence (UP/DOWN).

7.Synchronous Counter examples are: Ring counter, Johnson counter. Asynchronous Counter

examples are: Ripple UP counter, Ripple DOWN counter.

8.In synchronous counter, propagation delay is less.In asynchronous counter, there is high
propagation delay.

3. Ripple Counter

A counter is basically used to count the number of clock pulses applied to a flip-flop. It can
also be used for Frequency divider, time measurement, frequency measurement, distance
measurement and also for generating square waveforms. In this, the flip-flops are
asynchronous counters and are supplied with different clock signals, there may be a delay in
producing output.

Ripple counter –

A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter. It is
known as ripple counter because of the way the clock pulse ripples its way through the flip-
flops. Some of the features of ripple counter are:

It is an asynchronous counter.

Different flip-flops are used with a different clock pulse.

All the flip-flops are used in toggle mode.

Only one flip-flop is applied with an external clock pulse and another flip-flop clock is
obtained from the output of the previous flip-flop.

The flip-flop applied with external clock pulse act as LSB (Least Significant Bit) in the
counting sequence.

4. Binary up and Down Counter

Bidirectional Counter

Both Synchronous and Asynchronous counters are capable of counting “Up” or counting
“Down”, but their is another more “Universal” type of counter that can count in both
directions either Up or Down depending on the state of their input control pin and these are
known as Bidirectional Counters.
Bidirectional counters, also known as Up/Down counters, are capable of counting in either
direction through any given count sequence and they can be reversed at any point within their
count sequence by using an additional control input as shown below.
The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).
Generally most bidirectional counter chips can be made to change their count direction either
up or down at any point within their counting sequence. This is achieved by using an
additional input pin which determines the direction of the count, either Up or Down and the
timing diagram gives an example of the counters operation as this Up/Down input changes
state.
Nowadays, both up and down counters are incorporated into single IC that is fully
programmable to count in both an “Up” and a “Down” direction from any preset value
producing a complete Bidirectional Counter chip. Common chips available are the
74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronous Up/Down
binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.

5. ROM and its types

ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in
such memories during manufacture. A ROM stores such instructions that are required to start
a computer. This operation is referred to as bootstrap. ROM chips are not only used in the
computer but also in other electronic items like washing machine and microwave oven.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank
PROM and enters the desired contents using a PROM program. Inside the PROM chip, there
are small fuses which are burnt open during programming. It can be programmed only once
and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes.

Usually, an EPROM eraser achieves this function. During programming, an electrical charge
is trapped in an insulated gate region. The charge is retained for more than 10 years because
the charge has no leakage path. For erasing this charge, ultra-violet light is passed through a
quartz crystal window (lid). This exposure to ultra-violet light dissipates the charge. During
normal use, the quartz lid is sealed with a sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

EEPROM is programmed and erased electrically. It can be erased and reprogrammed about
ten thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In
EEPROM, any location can be selectively erased and programmed. EEPROMs can be erased
one byte at a time, rather than erasing the entire chip. Hence, the process of reprogramming is
flexible but slow.