MINI PROJECT DIGIT

COUNTER

INTRODUCTION:

A counter is a group of flip-flops connected together to perform counting operations. The

number of flip-flops used and the way in which they are connected determine the number of states
(modulus). According to the flip order of flip-flops, the counter can be devided into asynchronous
and synchronous.

Asynchronous counters are those counters which do not operate on simultaneous clocking.
In asynchronous counter, only the first flip-flop is externally clocked using clock pulse while the clock
input for the successive flip-flops will be the output from a previous flip-flop. This means that only a
single clock pulse is not driving all the flip-flops in the arrangement of the counter

Another name for Asynchronous counters is “Ripple counters”. The number of flip flops used
in a ripple counter is depends up on the number of states of counter ( Mod 4, Mod 2 ). The number
of output states of counter is called “Modulus” or “MOD” of the counter. The maximum number of
states that a counter can have is 2n where n represents the number of flip flops used in counter.

The synchronous counter is a type of counter in which the clock signal is simultaneously
provided to each flip-flop present in the counter circuit. More specifically, we can say that each flip-
flop is triggered in synchronism with the clock input. Unlike asynchronous counter where separate
clock pulses are used to trigger the flip-flop, all the flip-flops in synchronous counters are triggered
using a single clock pulse.

We know designing an asynchronous counter is easy then what is the reason behind
designing the synchronous counter. The answer to this question is that the asynchronous counter
has a limitation towards maximum operating frequency. Therefore, in order to overcome this
limitation, synchronous counters are designed in which simultaneous clocking is provided. Due to
simultaneous clocking, the output varies in synchronization with the clock input. Synchronization
leads to variation in each output bit at the same time with a common clock signal. Thereby
eliminating the ripple effects and so the propagation delay.
REGISTER

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the
storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-
flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of
storing an n-bit word.

 A shift register is a sequential logic circuit that acts as a unit to store and transfer binary
data. Basically shift registers are bidirectional FIFO circuit, that shifts every single bit of the data
present in its input towards its output on each clock pulse. We know registers are the circuits
constructed using flip-flops for storing binary data. One-bit of data is stored by each flip-flop at a
time. So, the storage of multiple bits of data requires multiple flip-flops.

Shift registers are formed by the serial combination of D flip-flops, where each flip-flop in the
arrangement holds single data bit. The serial arrangement permits the output of one flip-flop to act
as input to other and this allows the shifting of data bit inside the register.The binary data in a
register can be moved within the register from one flip-flop to another. The registers that allow such
data transfers are called as shift registers. There are four mode of operations of a shift register.

 Serial Input Serial Output (SISO)

 Serial Input Parallel Output (SIPO)

 Parallel Input Serial Output (PISO)

 Parallel Input Parallel Output (PIPO)

Serial Input Serial Output (SISO)

Let all the flip-flop be initially in the reset condition, example: Q 3 = Q2 = Q1 = Q0 = 0. If an
entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3, example: D 3 is connected to serial data
input Din. Output of FF-3, example: Q3 is connected to the input of the next flip-flop, example: D 2 and
so on.

Serial Input Parallel Output (SIPO)

 In such types of operations, the data is entered serially and taken out in parallel fashion.

 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.

 As soon as the data loading gets completed, all the flip-flops contain their required data, the
outputs are enabled so that all the loaded data is made available over all the output lines at
the same time.

 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO
mode is same as that of SISO mode.

Parallel Input Serial Output (PISO)

 Data bits are entered in parallel fashion.
 The circuit shown below is a four bit parallel input serial output register.
  Output of previous Flip Flop is connected to the input of the next one via a combinational
circuit.
 The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
 There are two modes in which this circuit can work namely - shift mode or load mode.

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2,
D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input binary bits
will be loaded into the flip-flops simultaneously. The loaded bits will appear simultaneously to the
output side. Only clock pulse is essential to load all the bits.
Bidirectional Shift Register
 If a binary number is shifted left by one position then it is equivalent to multiplying the
original number by 2. Similarly if a binary number is shifted right by one position then it is
equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and divide the given binary number,
then we should be able to move the data in either left or right direction.
 Such a register is called bi-directional register. A four bit bi-directional shift register is shown
in fig.
 There are two serial inputs namely the serial right shift data input DR, and the serial left shift
data input DL along with a mode select input (M).

PROBLEM STATEMENT:
JK Flip Flop
The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic
circuits but it suffers from two basic switching problems.
 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
 2. if Set or Reset change state while the enable (EN) input is high the correct latching action
may not occur.

This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered
to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated
letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters
chosen by its inventor Jack Kilby to distinguish the flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-
flop with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no
invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to
that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a clock input.

Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1” state to be
used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the
upper NAND gate. As Q and Q are always different we can use them to control the input. When both
inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in the following truth table.
D Flip Flop
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the
indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
This state will force both outputs to be at logic “1”, over-riding the feedback latching action
and whichever input goes to logic level “1” first will lose control, while the other input still at logic
“0” controls the resulting state of the latch.
But in order to prevent this from happening an inverter can be connected between the
“SET” and the “RESET” inputs to produce another type of flip flop circuit known as a Data
Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more
generally called.
The D Flip Flop is by far the most important of all the clocked flip-flops. By adding an
inverter (NOT gate) between the Set and Reset inputs, the S and R inputs become complements of
each other ensuring that the two inputs S and R are never equal (0 or 1) to each other at the same
time allowing us to control the toggle action of the flip-flop using one single D (Data) input.
Then this Data input, labelled “D” and is used in place of the “Set” signal, and the inverter is
used to generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop
from a level-sensitive SR-latch as now S = D and R = not D.
 We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and
one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET”
and “RESET” the flip-flop using just one input as now the two input signals are complements of each
other. This complement avoids the ambiguity inherent in the SR latch when both inputs are LOW,
since that state is no longer possible.
Thus this single input is called the “DATA” input. If this data input is held HIGH the flip flop
would be “SET” and when it is LOW the flip flop would change and become “RESET”. However, this
would be rather pointless since the output of the flip flop would always change on every pulse
applied to this data input.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the
data input from the flip flop’s latching circuitry after the desired data has been stored. The effect is
that D input condition is only copied to the output Q when the clock input is active. This then forms
the basis of another sequential device called a D Flip Flop.
The “D flip flop” will store and output whatever logic level is applied to its data terminal so
long as the clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the
flip-flop are both held at logic level “1” so it will not change state and store whatever data was
present on its output before the clock transition occurred. In other words the output is “latched” at
either logic “0” or logic “1”.
STATE DIAGRAM
In addition to graphical symbols, tables or equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the circles. An example of a state
diagram is shown in Figure 3 below.
 The binary number inside each circle identifies the state the circle represents. The directed
lines are labeled with two binary numbers separated by a slash (/). The input value that causes the
state transition is labeled first. The number after the slash symbol / gives the value of the output.
For example, the directed line from state 00 to 01 is labeled 1/0, meaning that, if the sequential
circuit is in a present state and the input is 1, then the next state is 01 and the output is 0. If it is in a
present state 00 and the input is 0, it will remain in that state. A directed line connecting a circle
with itself indicates that no change of state occurs. The state diagram provides exactly the same
information as the state table and is obtained directly from the state table.

Objective

The objective of doing this project :

1. To gain an experience on how to design counter circuit via state table and k map technique.

2. To gain knowledge about the way to create counter circuit from the beginning.

3. To simulate the counter circuit using Quartus II.

4. To understand the operation and characteristic of synchronous circuit.

5. To gain knowledge about types of register.

6. To understand the function of register used in the circuit.

7. To display the counting output using 7 segment.

8. To learn how counter will work with register in circuit.

9. To improve our creativity by designing this circuit by our own.

Scope Of Work

 There is no propagation delays associated with synchronous counter.

 With synchronous counter we can set the same clock pulse for all gates.
 Synchronous counter operation is faster
 Chances of errors are minimal due to the fact that count sequence is controlled using logic
gates.
 All flip flops in synchronous counter are driven by a single, common clock pulse.
 They require large components and circuitry than asynchronous counters.
 The design involves a complex logic circuit as well as the increasing number of states.
 Most seven-segment displays are limited to displaying the 16 hexadecimal characters
 Some can display only the numbers 0 through 9.
 Although LED technology exists to display more than this, seven-segment displays are
limited to possible binary combinations of the four input leads, for a total of 16
 Integrated circuit technology can increase this somewhat, but there are still a limited
number of combinations for the seven segments on the display.