4-bit Shift register
It is a sequential circuit which is used to store and transfer of binary data. It receives the data
from its inputs and store, then shifts it to its output for every clock pulse, hence the name shift
register. Shift Register is made of the number of individual Flip Flops. For example, a 4-bit
shift register is constructed from four individual FFs. Generally, shift registers operate in one
of four different modes with the basic movement of data through a shift register.
Types of shift registers
i) Serial in Serial out (SISO) Shift Register
ii) Serial in parallel out (SIPO) Shift Register
iii) Parallel in Serial out (PISO) Shift Register
iv) Parallel in Parallel out (PIPO) Shift Register
A typical 4-bit shift register is shown below.
Serial-in Serial-out (SISO)
The “Preset-enable” should be held at logic‘0’. The input is fed in serially to “Serial in” and
output is read serially out on “Serial out” (Q0). During each clock pulse, one bit of input data
is transmitted from left to right (FF3 to FF0). Assume that initially all flip-flops are cleared
(Q3 = Q2 = Q1 = Q0 = 0). For example, let us consider input data (0101) has to be shifted
through the register from FF3 to FF0. Least significant bit (1) is passed first and most
significant bit (0) is passed last to FF3. The SISO operation is demonstrated in the table
below (unused states are shown as NULL). It takes seven clock pulses to complete the read
operation.
Serial-in Parallel-out (SIPO)
The “Preset-enable” should be held at logic‘0’. The input is fed in serially to “Serial in” and
output is read simultaneously out on Q3Q2Q1Q0. During each clock pulse, one bit of input
data is transmitted from left to right (FF3 to FF0). The SIPO operation for the same example
(0101) is demonstrated in the table below (unused states are shown as NULL). It takes four
clock pulses to complete the read operation.
Parallel-in Parallel-out (PIPO)
The input is fed in simultaneously to D3D2D1D0 and output is read simultaneously out on
Q3Q2Q1Q0. Assume that initially all flip-flops are cleared (Q3 = Q2 = Q1 = Q0 = 0). For
parallel-in operation, “Preset-enable” should be set.
“Preset-enable” D input NAND gate output Action
1 0 1 FF output will not be Preset
1 1 0 FF output will be Preset
As soon as the “Preset-enable” is set i.e., logic‘1’, the outputs will be Q3=D3, Q2 =D2,
Q1=D1 and Q0=D0. No clock pulse is required.
Parallel-in Serial-out (PISO)
The input is fed in simultaneously to D3D2D1D0 and output is read serially out on “Serial
out” (Q0). Assume that initially all flip-flops are cleared (Q3 = Q2 = Q1 = Q0 = 0). As soon
as the “Preset-enable” is set i.e., logic‘1’, the outputs will be Q3=D3, Q2 =D2, Q1=D1 and
Q0=D0. After three more clock pulses the read operation is completed.
Bidirectional shift register
Bidirectional shift registers are the storage devices which are capable of shifting the data
either right or left depending on the mode selected. Figure shows a 4-bit bidirectional shift
register with serial data loading and retrieval capacity. Initially all the flip-flops in the register
are reset. Right/¿ ¿ control line is made either low or high in order to opt for either left-shift or
right-shift of the data bits, respectively.
Right shift operation
Let us consider that the data is fed in serially to the leftmost flip-flop. If Right/ ¿ ¿= 1, then
G1 , G2 , G3 and G4 gates of all the combinational circuits get activated while the G 5 , G6 , G7
and G8 gates will get disabled (i.e., the output will be 0 irrespective of the other input) at the
same time. Due to this, the outputs of previous flip-flop (except for the last flip-flop) appear
at the inputs of the very-next flip-flop via OR gate output i.e.,
‘Serial-in’ appears at D0 via the output of OR gate O0,
Q0 appears at D1 via the output of OR gate O1,
Q1 appears at D2 via the output of OR gate O2,
Q2 appears at D3 via the output of OR gate O3.
At this instant, if a clock pulse is applied, the outputs of the respective flip-flops reflect their
inputs. Thus the updated outputs will be Q0 = D0, Q1 = D1, Q2 = D2, and Q3 = D3. For every
clock pulse, the data within the register shifts right by a single bit as long as Right/¿ ¿ remains
high.
Left shift operation
Let us consider that the data is fed in serially to the rightmost flip-flop. If Right/ ¿ ¿= 0, then
G1 , G2 , G3 and G4 gates of all the combinational circuits get disabled (i.e., the output will be
0 irrespective of the other input) while the G 5 , G6 , G7 and G8 gates will get activated at the
same time. Due to this, the outputs of subsequent flip-flop (except for the first flip-flop)
appear at the inputs of the previous flip-flop via OR gate output i.e.,
‘Serial-in’ appears at D3 via the output of OR gate O3,
Q3 appears at D2 via the output of OR gate O2,
Q2 appears at D1 via the output of OR gate O1,
Q1 appears at D0 via the output of OR gate O0.
At this instant, if a clock pulse is applied, the outputs of the respective flip-flops reflect their
inputs. Thus the updated outputs will be Q0 = D0, Q1 = D1, Q2 = D2, and Q3 = D3. For every
clock pulse, the data within the register shifts left by a single bit as long as Right/¿ ¿ remains
low.
An example is shown in the table below.
