Flip-Flops and Its Applications: Module - 3

Digital System Design (18EC34)
Module -3
Flip-Flops
and its Applications
Topic Section
 Basic Bistable elements 6.1
 Latches 6.2
 The master-slave flipflops (pulse-triggered flip-flops): 6.4
o SR flip-flops 6.41,6.42
o JK flip-flops
 D FF, T FF
 Characteristic equations 6.6
 Registers 6.7
 binary ripple counters 6.8.1
 synchronous binary counters 6.8.2
(Text 2 - Chapter 6)
2. Donald D. Givone, ―Digital Principles and Design, McGraw Hill, 2002.
Module 3/RNSIT/ECE Page 1

Introduction
Combinational and Sequential Circuits
The two types of Digital circuits depend on their output and memory used:
(i) Combinational circuit: Consists of logic gates whose outputs at any time are determined
from only the present combination of inputs and they have no memory. The output at
any time is a direct function of the applied external inputs as shown in Fig.3.1.
Fig.3.1 Combinational Circuit
Drawbacks of Combinational circuits:

If a system needs to be designed that stores and uses previous input and output, then
combinational circuits cannot be used as it doesn’t have capability to store any state or
depend on clock or and time. For these properties Sequential circuits can be used.
(ii) Sequential circuit: Consists of logic gates whose outputs at any time are determined
from both the present combination of inputs and previous output. That means
sequential circuits use memory elements to store the value of previous output. The
block diagram of sequential circuit is shown in Fig.3.2
Fig.3.2 Sequential Circuit
Difference between Characteristics of Combinational and Sequential circuits

S.NO. COMBINATIONAL CIRCUITS SEQUENTIAL CIRCUITS
The output depends only on the The output depends upon both present
present input and there is no need input and present state (previous output),
for feedback for input and output, so memory element is required to save
1 so memory element is not required. the feedback state.
2 It is easier to design, use and It is not easier to design, use and handle

S.NO. COMBINATIONAL CIRCUITS SEQUENTIAL CIRCUITS
handle. than combinational circuits.
Clock signals are required and it is

Clock signals are not required and it dependent on time and clock so need
3 is not dependent on time. triggering.
Elementary building blocks are logic

4 gates Elementary building blocks are Flip-Flops
These circuits are slower than

5 These are faster logic circuits. combinational circuits.
Storage Elements:
Generally, there are two types of storage elements used: Latches, and Flip-Flops.
 Storage elements that operate with signal levels (rather than signal transitions) are
referred to as Latches.
 Storage elements that are controlled by a clock transition are called Flip-Flops.
3.1 Basic Bistable element:

One Bit memory cell is also called Basic Bistable element. It has two cross-coupled
inverters, 2 outputs Q and Q’. It is called “Bistable” as the basic bistable element circuit has
two stable states logic 0 and logic 1. The Fig. 3.3 shows the basic bistable element.
It can be seen that the output of first not gate serves as the input to the second and the
output of second not gate serves as the input to the first.
Fig.3.3 Basic Bistable Element
The working of the bistable element

(A) when A=0,
(i) In inverter1, Q = A'= B= 1 Q = 1, Q’= 0
(ii)In inverter2, Q' = B' = A = 0
The latch is always in a stable state
(B) when A=1,
(i) In inverter1, Q = A'= B= 0
(ii)In inverter2, Q' = B' = A = 1 Q = 0, Q’= 1
Observation:
1. The two outputs are always complementary.
2. The circuit has 2 stable states.

 When Q=1, it is Set state. [Normal output]

 When Q=0, it is Reset state. [Complementary output]
3. The circuit can store 1-bit of digital information and so it is called one-bit memory cell.
4. The one-bit information stored in the circuit is locked or latched in the circuit. This
circuit is also called Latch.
Flip-Flop :
Flip-flop is a basic digital memory circuit, which stores one bit of information. A flip-flop is a
bistable device with inputs, that remains in a given state as long as power is applied and until
input signals are applied to cause its output to change. It consists of a basic bistable element
in which appropriate logic is added in order to control its state.
The process of storing a 1 into a flip-flop is called Setting or Presetting the flip-flop; while the
process of storing a 0 into a flip-flop is called Resetting or Clearing the flip-flop.
The inputs to a flip-flop are of two types. An asynchronous or direct input is one in which a
signal change of sufficient magnitude and duration essentially produces an immediate change
in the state of the flip-flop. On the other hand, a synchronous input does not immediately
affect the state of the flip-flop, but rather affects the state of the flip-flop only when some
control signal, usually called an enable or clock input, also occurs.
Flip flops are the fundamental blocks of most sequential circuits. Flip-flops are used as
memory elements in sequential circuit. It is also known as a bistable multivibrator or a binary
or one-bit memory.
Difference between Flip-flop and Latch
NO FLIP-FLOP LATCH
Flip-flop is a bistable device. It has two Latch is also a bistable device whose
1 stable states represented as 0 and 1. states are represented as 0 and 1.
It checks the inputs but changes the It checks the inputs continuously and
output only at times defined by the responds to the changes in inputs
2 clock signal or any other control signal. immediately.
3 It is an edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND are

4 building blocks of flip flops. These are also made up of logic gates.
They are classified into asynchronous or There is no such classification in

5 synchronous flip-flops. latches.
It forms the building blocks of many Can be used to design sequential

6 sequential circuits like counters. circuits but are not preferred.
7 Flip-flop always have a clock signal Latches doesn’t have a clock signal
8 Flip-flop can be built from Latches Latches can be built from gates

3.2 Latches
The storage devices called latches form one class of flip-flops. This class is characterized by
the fact that the timing of the output changes is not controlled. That is, the output
essentially responds immediately to changes on the input lines, although a special control
signal, called the enable or clock might also need to be present. Thus, the input lines are
continuously being interrogated
3.2.1 The SR Latch (Set- Reset Latch)

Fig 3.4(a) shows SR Latch, which consists of two cross-coupled NOR gates. It has two inputs,
̅.
S and R, referred to as the set and reset inputs, and two outputs, Q and Q
In the function table shown in Fig 3.4 (b), Q denotes the present state of the latch. Q is the
state of the device at the time the input signals are applied. The response of the latch at the
Q and 𝑄̅ output terminals as a consequence of applying the various inputs is denoted by Q+
and 𝑄̅+, respectively. Thus, Q+ is called the next state of the latch. SR latch using NOR gates is
an active high input SR latch.
Inputs Outputs
S R Q+ 𝐐 ̅+
0 0 Q ̅
Q
0 1 0 1
1 0 1 0
1 1 0* 0*
*Unpredictable behaviour
will result if inputs return
Fig. 3.4 (a)
to 1 simultaneously
Fig 3.4 (b)
Fig 3.4 (c)
Working of SR Latch
Case 1:
When S = R = 0, the output remains in previous state i.e. it holds the previous data as shown
in first row of the function table given in below Fig 3.4 (b)
Case 2:
When S=0 and R=1, the latch will be in RESET state. Because the high input of NOR gate with
R input drives the other NOR gate with 0, as its output is 0. So both the inputs of the NOR
gate with S input are 0. This will cause the output of the latch to settle in RESET state (Q+=0).

Fig 3.5
Case 3:
When S=1 and R=0, then the latch will be in SET state (Q+=1). The low input of NOR gate
with S input drives the other NOR gate with 1, as its output is 1. So both the inputs of the
NOR gate with R input are 1. This will cause the output of the latch to settle in SET state as
shown in Fig. 3.6.
Fig.3.6
Case 4:
When both the S = R = 1, the latch will be in undefined state. The high inputs of S and R,
violates the rule that the outputs should complement to each other. So the latch is in
undefined state (or forbidden state). The output of SR latch for various input conditions is
shown in Fig. 3.7
Fig. 3.7
The problem with simple SR latch is that they are level sensitive, which makes them a
transparent device. In order to avoid this, Gated or Clocked SR flip – flops are used. Clock
signal makes the device edge sensitive (and hence no transparency).
3.2.2 The 𝑺̅ 𝑅̅ Latch

𝑺̅ 𝑅̅ Latch is constructed by cross-coupling two NAND gates as shown in Fig. 3.8. It is
an active low input SR Latch.
Inputs Outputs
𝑺̅ 𝑅̅ Q+ 𝐐̅+
0 0 1* 1*
0 1 1 0
1 0 0 1
1 1 Q ̅
Q
*Unpredictable behaviour will result if
inputs return to 0 simultaneously
Fig 3.8 (a) Fig 3.8 (b)

Fig 3.8 (c)
Working
Case 1:
When S̅ = R
̅ = 1, then the output remains in previous state i.e. it holds the previous data.
Case 2:
When S̅ = 1 and R̅ =0, then the latch will be in RESET state. The low input of NAND gate with
̅
R input drives the other NAND gate with 1, as its output is 1. So both the inputs of the NAND
gate with S̅ input are 1. This will cause the output of the latch to settle in RESET state.
Case 3:
When S̅ =0 and R ̅ = 1, then the latch will be in SET state. Because the low input of NAND
gate with S̅ input drives the other NAND gate with 1, as its output is 1. So both the inputs of
the NAND gate with R input are 1. This will cause the output of the latch to settle in SET
state.
Case 4:
When both the 𝑆̅ = 𝑅̅ = 0, then the latch will be in undefined state. The low inputs of 𝑆̅ and
𝑅̅, violates the rule that the outputs should compliment to each other. So the latch is in
undefined state (or forbidden state).
Ex:1 For the given value of S and R inputs in Fig 3.9, plot Q and 𝑄̅
3.2.3 An Application of the SR Latch: A Switch Debouncer

Mechanical switches, when pressed or released, often take some time and vibrate several
times before settling down. This non – ideal behaviour of the switch is called switch bounce
or mechanical bounce. This mechanical bounce will tend to fluctuate between low and high
voltages which can be interpreted by digital circuit. This can result in variation of pulse
signals and these series of unwanted pulses will result in the digital system to work
incorrectly.

Fig. 3.9
For example, in this bouncing period of the signal, the fluctuations in the output voltage are
very high and therefore the register counts several inputs instead of single input. To
eliminate this kind of behavior of digital circuits, we use SR flip – flops.
For interfacing keys to the digital systems, usually push bottom keys are used. These push
button keys when pressed bounces a few times, closing and opening the contacts before
providing a steady reading, as shown in the Fig. (a). Reading taken during bouncing period
may be faulty. This problem is known as key debounce. The problem of key debounce is
undesirable and it must be avoided.
One way to avoid key debounce problem is to use SR latch. The circuit used to avoid
keybounce with SR latch is called a switch debouncer. The Fig. (b) shows the switch
debouncer circuit and its waveforms. When key is at position A, the output of SR latch is
logic 1, and when key is at position B, the output of SR latch is logic 0. It is important to note
that, when key is in between A and B, SR inputs are 00 and hence output does not change,
preventing debouncing of key output. In other words, we can say that the output does not
change during transition period, eliminating key debounce.

The Gated SR Latch The inputs for both the SR latch and the S’R’ latch are asynchronous (or
direct). That is, a change in value of these inputs causes an immediate change of the
outputs. It is frequently desirable to prevent input activation signals from affecting the state
of the latch immediately, but rather to have the effect occur at some desirable time or
alternatively, to allow the input changes to be effective only during a prescribed period of
time. For these situations, a gated SR latch is used. The gated SR latch is also called an SR
latch with enable. A gated SR latch is shown in below Fig. It consists of the SR latch along
with two additional nand-gates and a control input, C, referred to as the enable, gate, or
clock input. The enable input, C, determines when the S and R inputs become effective. As
shown by truth table, the circuit behaves like a SR latch when EN = 1, and retains its
previous state when EN= 0.
Inputs Outputs
S R C Q+ 𝐐̅+
0 0 1 Q ̅
Q
0 1 1 0 1
1 0 1 1 0
1 1 1 1* 1*
(a) x x 0 Q ̅
Q
Unpredictable behaviour will result if inputs
return to 1 simultaneously or C returns to 0
while S and R are 1
(b)

The Gated D Latch

The three latches discussed thus far each has an input combination that is not
recommended. In particular, the situation in which both of the non-control inputs, i.e., Sand
R or Sand R, are simultaneously active. The gated D (or data) latch, whose logic diagram and
function table are shown in Fig.a-b, does not have this problem. The gated D latch is a gated
SR latch in which a not-gate is connected between the S and R terminals. Thus, the latch
consists of a single input D that determines its next state and a control, i.e., enable, input C
that determines when the D input is effective. As indicated in the function table, when the
latch is enabled, i.e., C = 1, the output of the latch follows the values applied to the D input
terminal. In particular, if D = 0, then the latch switches to or remains in the 0-state; while if
D = 1, then the latch switches to or remains in the 1-state. However, when the latch is
disabled, i.e., C = 0, the latch remains in the state prior to the enable signal going to 0
Inputs Outputs
D C Q+ ̅+
𝐐
0 1 0 1
1 1 1 0
X 0 Q ̅
𝐐
(C)
Working :
In the above figure ,we have a Gated SR Latch implemented using NAND gates.NAND implementation is used
because will take less number on transistors.
The D input is given to S and D_bar ( ie.,NOT D) is given to R.Here we will not have the problem of latch going
to forbidden state (ie., S=1 and R=1)
because inputs to this latch is reversed (ie., in SR latch first input is R and second is S but here it is reversed).
Lets Assume some value for the output Q (ie., 0 here) and proceed with it working.
Q='0' , Clk='0' and D='x' :-
S' = Clk (nand) S

R' = Clk (nand) R
Q = Q_bar (nand) S'
Q_bar = Q (nand) R'
Q= '0' assumed => Q_bar='1'
Q='0' , Clk='1' and D='0/1' :-
S' = Clk (nand) S

R'= Clk (nand) R
Q = Q_bar (nand) S'
Q_bar = Q (nand) R'
Q= '0' assumed => Q_bar='1'

Table :
Outputs for all combination of inputs and assumed values of Q.
3.3 TIMING CONSIDERATIONS

The function tables for the various latches introduced specify the state outputs as a result
of applying the input signals. However, the responses to the inputs are not really
immediate, but rather occur after some appropriate time delay. This is due to the time
delays associated with the gates themselves. Furthermore, to achieve the desired
responses, certain timing constraints must normally be satisfied. These timing constraints
are presented in this section with reference to latches; however, they also pertain to the
additional types of flip-flops that are discussed in the next two sections.
A convenient way of showing the terminal behavior of a flip-flop is the timing diagram. A
timing diagram is a graph that depicts the input and output transitions of a flip-flop as a
function of time. Propagation Delays The propagation delay is the time it takes a change in
an input signal to produce a change in an output signal. In general, the propagation delay
between each pair of input and output terminals is different, as well as whether the
change causes the output to go from low to high, i.e., from 0 to 1 in positive logic, or from
high to low, i.e., from 1 to 0 in positive logic. The various propagation delays of a flip-flop
are specified by the manufacturer. Propagation delays in an SR latch are illustrated in
fallowing figure. This figure shows the effect of first setting and then resetting an SR latch.
It should be noted that the outputs do not change instantaneously to an input change nor
do the outputs change simultaneously. tpLH = the propagation delays from low to high,
i.e., from 0 to 1 in positive logic. tpHL= the propagation delays from high to low, i.e., from
1 to 0 in positive logic. tpLH and tpHL are, in general, different as well as whether the Q or
𝑄 ̅ output terminals are being viewed.
The propagation delay is the time it takes a change in an input signal to produce a change in an
output signal.
• Propagation delay from low to high: 𝑡𝑝𝐿𝐻
• Propagation delay from high to low: 𝑡𝑝𝐻

Figure below shows the outputs of an SR latch as various signal values are applied to the S and R
inputs. For simplicity, the finite slopes of the rising and falling edges of the signals are not shown and
the propagation delays are assumed to be all equal. It should be noted in the figure that when S = R
= 1, both the Q and 𝑄 ̅ outputs become 0.
In addition, special attention should be given to the response of the latch at time t15. Here it is
assumed that the signals on the S and R input terminals are simultaneously changed from 1 to 0. As
a consequence, the response of the latch is unpredictable as indicated by the shaded area.
The latch may be in its 0-state, 1-state, or metastable state. At time t16, however, the application of
the 1 on the set input terminal returns the latch to predictable behavior after a short propagation
delay time.
Inputs Outputs
S R Q+ 𝐐̅+
0 0 Q ̅
Q
0 1 0 1
1 0 1 0
1 1 0* 0*
Fig 3.

Propagation delays from high-low, low-high assumed equal.

• When S = R = 1, both 𝑄, become 0.
• 𝑡15, signals on S, R are simultaneously changed from 1 to 0.
– Response of latch is unpredictable. Can be in 0-state, 1-state or metastable state.
– Application of 1 on the set input terminal returns the latch to predictable.
3.3.2 Minimum Pulse Width

Another specification stated by the manufacturers of latches is that of a minimum pulse
width tw(min). This is the minimum amount of time a signal must be applied in order to
produce a desired result. Failure to satisfy this constraint may not cause the intended
change or possibly have the latch enter its metastable state. In either event unpredictable
behavior results. The minimum pulse width constraint is illustrated in following figure
Fig 3.
3.3.3 Setup and Hold Times

A timing diagram for a gated D latch with function table is shown in below
figure.
Fig. 3.

In accordance with the function table, and as illustrated in the figure, the Q-
output of the latch follows the input signal at the D terminal whenever the
enable signal, C, is 1. Whenever the enable signal is 0, changes at the D
terminal are ignored and the Q-output retains the state of the latch just prior to
the l to 0 change in the enable signal.
To achieve this operation of a gated latch, constraints are normally placed on
the time intervals between input changes.
Consider times t3, t6, t11, and t14, at these times the enable signal t is returned to
0, causing the output to latch onto its current state.
However, to guarantee this latching action, a constraint is placed upon the D
signal for some minimum time before and after the enable signal goes from 1 to
0. This is shown as the shaded areas in above figure.
For proper operation, the D signal must not change during this period. The
minimum time the D signal must be held fixed before the latching action, tsu is
called the setup time; while the minimum time the D signal must be held fixed
after the latching action, th, is called the hold time.
Failure to satisfy the setup time and hold time constraints can result in
unpredictable output behavior, including metastability. This is illustrated in
following figure, where unpredictable behavior occurs when latching is
attempted at time t12 since the signal on the D line changed at time t11, which is
assumed to have occurred within the setup time of the gated D latch.
Setup and hold time constraints are very important properties when
considering the behavior of all types of flip-flops.
Fig
JK and T Flip-Flops
A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state of the RS type
is defined in the JK type. Inputs J and K behave like inputs Sand R to set and clear the flip-
flop, respectively. The input marked J is for set and the input marked K is for reset. When

both inputs J and K are equal to 1, the flip-flop switches to its complement state, that is, if Q
= 1, it switches to Q = 0, and vice versa.
A JK flip-flop constructed with two cross-coupled NOR gates and two AND gates is shown
in Fig. 6-6(a). Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during
a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed with J and CP inputs
so that the flop-flop is set with a clock pulse only when Q' was previously 1. When both J and
K are 1, the input pulse is transmitted through one AND gate only: the one whose input is
connected to the flip-flop output that is presently equal to 1.
Thus, if Q = 1, the output of the upper AND gate becomes 1 upon application of the clock
pulse, and the flip-flop is cleared. If Q' = 1, the output of the lower AND gate becomes 1 and
the flip-flop is set. In either case, the output state of the flip-flop is complemented. The
behavior of the JK flip-flop is demonstrated in the characteristic table of Fig. 6-6(b).
It is very important to realize that because of the feedback connection in the JK flipflop, a CP
pulse that remains in the 1 state while both J and Kare equal to 1 will cause the output to
complement again and repeat complementing until the pulse goes back to 0.
A JK flip-flop has two inputs similar to that of RS flip-flop. We can say JK flip-flop is a
refinement of RS flip-flop. JK means Jack Kilby, a Texas instrument engineer who
invented IC. The two inputs of JK Flip-flop is J (set) and K (reset). A JK flip-flop is nothing
but a RS flip-flop along with two AND gates which are augmented to it.
The flip-flop is constructed in such a way that the output Q is ANDed with K and CP. This
arrangement is made so that the flip-flop is cleared during a clock pulse only if Q was
previously 1. Similarly Q’ is ANDed with J and CP, so that the flip-flop is cleared during a
clock pulse only if Q’ was previously 1.
When J=K=0
When both J and K are 0, the clock pulse has no effect on the output and the output of
the flip-flop is the same as its previous value. This is because when both the J and K are
0, the output of their respective AND gate becomes 0.
When J=0, K=1
When J=0, the output of the AND gate corresponding to J becomes 0 (i.e.) S=0 and R=1.
Therefore Q’ becomes 0. This condition will reset the flip-flop. This represents the RESET
state of Flip-flop.
When J=1, K=0
In this case, the AND gate corresponding to K becomes 0(i.e.) S=1 and R=0. Therefore Q
becomes 0. This condition will set the Flip-flop. This represents the SET state of Flip-flop.
When J=K=1
Consider the condition of CP=1 and J=K=1. This will cause the output to complement
again and again. This complement operation continues until the Clock pulse goes back
to 0. Since this condition is undesirable, we have to find a way to eliminate this

condition. This undesirable behavior can be eliminated by Edge triggering of JK flip-flop

or by using master slave JK Flip-flops.
The characteristic table explains the various inputs and the states of JK flip-flop.
T flip-flops are similar to JK flip-flops. T flip-flops are single input version of JK flip-flops.
This modified form of JK flip-flop is obtained by connecting both inputs J and K together.
This flip-flop has only one input along with Clock pulse. These flip-flops are called T flip-
flops because of their ability to complement its state (i.e.) Toggle. So they are called as
Toggle flip-flop.
When T=1 and CP=1, the flip-flop complements its output, regardless of the present
state of the Flip-flop. In this case the next state is the complement of the present state.
When T=0, there is no change in the state of the flip-flop (i.e.) the next state is same as
the present state of the flip-flop. From the characteristic table and characteristic
equation it is quite evident that when T=0, the next sate is same as the present state.
Applications Of Flip-Flops
• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers
These are the various types of Flip-flops which are being used in Digital
electronic circuits and the applications of Flip-flops are as specified above.
To avoid this undesirable operation, the clock pulse must have a time duration that is
shorter than the propagation delay time of the flip-flop. This is a restrictive requirement,
since the operation of the circuit depends on the width of the pulse. For this reason, JK flip-
flops are never constructed as shown in Fig. 6-6(a). The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered construction, as discussed in the next
section. The same reasoning applies to the T flip-flop.

3.4 MASTER-SLAVE FLIP-FLOPS (PULSE-TRIGGERED FLIP-FLOPS)
In addition to latches, there are two other general categories of flip-flops.

These are the master-slave flip-flops (also called pulse-triggered flip-flops) and
the edge triggered flipflops

The latches have the common property of immediate output responses (to
within the propagation delay times) while enabled caused by changes on the
information input lines, i.e., the S, R, and D lines. This property is referred to as
transparency. In certain applications, this is an undesirable property. Rather, it
is necessary that the output changes occur only coincident with changes on a
control input line. This is particularly the case when it is necessary to sense the
current state of a flip-flop while simultaneously allowing new state information
to be entered as determined by the information lines. The property of having
the timing of a flip-flop response being related to a control input signal is
achieved with master-slave and edge-triggered flip-flops. A master-slave flip-
flop consists of two cascaded sections, each capable of storing a binary symbol.
The first section is referred to as the master and the second section as the
slave. Information is entered into the master on one edge or level of a control
signal and is transferred to the slave on the next edge or level of the control
signal. In its simplest form, each section is a latch.
The Master-Slave SR Flip-Flop

Figure below shows the master-slave SR flip-flop as constructed from two
gated SR latches and an inverter. The timing behavior of the master-slave flip-
flop is referenced to the control signal.
(a)

(b)
Fig.3.
The transition of the control signal from its low to high value, i.e., 0 to 1 in
positive logic, is called the rising, leading, or positive edge of the control signal;
while the transition of the control signal from its high to low value, i.e., 1 to 0
in positive logic, is called the falling, trailing, or negative edge of the control
signal. As long as C = 0 the master, being a gated SR latch, is disabled and any
changes on the S and R input lines are ignored. At the same time, the slave is
enabled due to the presence of the inverter. Hence, the slave is in the same
state as that of the master since the QM and 𝑄 ̅M outputs of the master are
Connected to the S and R inputs, respectively, of the slave. As the control
signal starts to rise, the slave is disabled, by design, at time t1; while the
master remains disabled. Thus, the slave becomes disconnected from the
master but retains the state of the master. The control signal continues to rise,

and it is at time t2 that the master is enabled. While C = 1; the master, being a
gated SR latch, responds to the inputs on the S and R lines, Meanwhile, since
the slave is disabled due to the presence of the inverter, any changes to the
state of the master are not reflected to the slave.
The control signal is subsequently returned to its low level at time t3. At this
time, the master is disabled, causing it to latch onto its new state. However, it
is not until time t4 that the slave is enabled. This results in the slave taking on
the state of the master as the connection is made. It is important to note that
for very short periods during the rising and falling edges of the control signal
both the master and slave latches are disabled. This is critical to the operation
of a master-slave flip-flop. It should be observed that although the master can
change its state (and, correspondingly, its output) at any time while the control
signal is 1, it is only as the control signal goes from 1 to O that the slave
changes its state. Thus, the output change of the master-slave flip-flop is
synchronized to the falling edge of the control signal.
The behavior of the master-slave SR flip-flop is summarized by the function

table in above Fig. The pulse symbol in the C column, indicates that the master
is enabled while the control signal is high and that the state of the master is
transferred to the slave, and, correspondingly, to the output of the flip-flop, at
the end of the pulse period. Since the behavior of master-slave flip-flops
constructed from latches is dependent upon the rising and falling edges of the
control signal as well as the period of time in which the control signal is high,
they are also referred to as pulse-triggered flip-flops. Figure below shows a
timing diagram for the input and output terminals of a master-slave SR flip-flop
along with a timing diagram for the output terminals of the master section of
the flip-flop.

Fig.3.
The Master-Slave JK Flip-Flop
S-R Clocked Flip-Flop

Subsystem
(a)

Fig 3.
Since the output state of a master-slave SR flip-flop is undefined upon returning

the control input to 0 when S = R = 1, it is necessary to avoid this condition. The
masterslave JK flip-flop, on the other hand, does allow its two information input
lines to be simultaneously 1. This results in the toggling of the output of the
flip-flop. That is, if the present state is 0, then the next state is 1; while if the
present state is 1, then the next state is 0.
Operation:
Case I: When clock is not given, both master and slave are inactive and there
will be no change in outputs.
Case II: For clock=1, master is active, slave inactive. As J=K=0, output of
master ie Q and Q' will not change. As soon as clock goes to 0, slave becomes
active, and master inactive. But since input to slave S and R is same, output of
slave will also remain same.
Case III: For clock=1, master is active and slave is inactive. When J=0 and
K=1, outputs of master will be Q=0, Q'=1, which will be inputs to slave. When
clock=0, slave becomes active and takes inputs 0,1 to give output Q=0, Q'=1.
This output will not change if clock is again made 1and then 0. Hence we get a
stable output from master and slave.
Case IV: For clock=1, master is active and slave is inactive. When J=1 and
K=0, outputs of master will be Q=1, Q'=0, which will be inputs to slave. When
clock=0, slave becomes active and takes inputs 1,0 to give output Q=1, Q'=0.
This output will not change if clock is again made 1 and then 0. Hence we get a
stable output from master and slave.
Case V: When clock =1, J=K=1, master output will toggle. So S and R will invert.
But slave remains inactive all this time since clock is 1. As soon as clock
becomes 0, slave becomes active and master becomes inactive. So slave will
also toggle. These changed outputs are returned through feedback to the
master, but master does not respond to them because clock is now 0 and
master is inactive. Thus, in one clock period, master and slave both toggle only
once, avoiding race condition caused by multiple toggling.

3.4.3 O's and 1 's Catching
The master of the master-slave JK flip-flop, being a latch, is enabled during the entire
period the control signal is 1.
O's Catching:
If the slave latch is in its 1-state, then a logic-1 on the K input line while the
control signal is 1 causes the master latch to reset. This subsequently results in the
slave becoming reset when the control signal returns to 0. An example of this occurred
during the second clock pulse in Fig. 3.15. This behavior is known as O's
catching.
[It should be noted that once the master latch is reset by a logic-1 signal on
the K input line, a subsequent logic-1 signal on the J input line during the same period
in which C = 1 does not cause the master to again become set. This is due to the
fact that since the slave does not change its state until C returns to 0, the feedback
signal from the slave, i.e., Qs = 0, keeps the output of the J-input and-gate at logic-0.]
1 's Catching
If the slave is storing a O, then a logic-1 on the J input line while the control signal is
1 causes the master latch to be set, which subsequently results in the setting of the
slave upon the occurrence of the falling edge of the control signal. This behavior
occurred during the third clock pulse in Fig. 3.15 and is known as l's catching.
Solution to 0’s and 1 's Catching

The O's and l's catching behavior is undesirable. Hence,

a) It is normally recommended that the J and K input values to be held fixed

during the entire interval that the master is enabled. To satisfy this constraint,
any changes in the J and K inputs must occur while the control signal is 0.
b) The problem of O's and l's catching is also solved by the use of edge-triggered
flip-flops where the master responds during the +ve or rising edge of the clock
and the state of the master transferred to slave at the –ve or falling edge of the
clock.
c) The master-slave flip-flop with data lockout.
3.4.4 Additional Types of Master-Slave Flip-Flops

From the master-slave SR and JK flip-flops, additional types of master-slave
flip-flops can be constructed. For example, by placing an inverter between the S
and R inputs of a master-slave SR flip-flop, as shown in Fig. below, a master-
slave D flip-flop is obtained.
(a) (b)
Fig. 3. Master-slave D flip-flop. (a) Logic diagram using a master-slave SR flipflop.
(b) Two logic symbols.
Having designed the system, our next step is to verify its functionality by
using an SR-to-D verification table as shown in Figure 6
Figure 6: Comparison between an SR-to-D verification table and the truth table of D flip-flop
From the verification table shown in Figure 6, it is evident that the entries in its first,
second, and sixth columns (shaded in beige) are identical to the entries found in the
truth table of the D flip-flop. This indicates that the system designed using the given
SR flip-flop will behave exactly as a D flip-flop.

Another type of master-slave flip-flop is shown in Fig. below, where the J and K
input· terminals are tied together so that T = J = K. In this case the flip-flop
changes state, or toggles, with each control pulse if T = 1 and retains its current
state with each control pulse if T = 0. This is called a master-slave T flip-flop.
The function table of the master-slave T flip-flop and its logic symbols are given
in below Fig.
Figure 3. Master-slave T flip-flop. (a) Logic diagram using a master-slave JKflip-flop.

(b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.
3.5.4 Additional Types of Edge-Triggered Flip-Flops
Figure 3.23 Positive-edge-triggered Tflip-flop. (a) Logic diagrams. (b) Function table where
Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

3.6 CHARACTERISTIC EQUATIONS

Three classes of flip-flops have been presented in this chapter: latches, pulse-
triggered flip-flops, and edge-triggered flip-flops. The timing scheme utilized
by the flip-flops served as the basis for the classifications.
The first class of flip-flops consisted of the latches. This class is characterized
by their outputs responding immediately at all times while enabled.
The second class was the pulse-triggered flip-flops using the master-slave
structure. In this class, information enters the master on the first edge of the
control signal, in the case of those with data lockout, or during an entire pulse
period, in the case of those without data lockout. In both cases, the content of
the master is transferred to the slave at the time of the second edge of the
triggering pulse.
Thus, this class of flip-flops is characterized by the outputs being postponed
until the end of the triggering pulse period.
In the third class of flip-flops, i.e., the edge triggered flip-flops, inputs from the
information lines are accepted only upon the occurrence of one of the control
input edges. At all other times, the information inputs are effectively
disconnected. Thus, the control' input edge serves to sample the information
input lines. The outputs of edge-triggered flip-flops respond immediately.
The four types of flip-flops that have been described in this chapter are the SR
flip-flop, the JK flip-flop, the D flip-fopp, and the T flip-flop. Simplified forms
of their function tables are given below
A variation of the simplified function tables, called the next-state tables, for
the four types. of flip-flops. The next-state tables show the value of the next
state of the flip-flops for each combination of values to the present state of the
flip-flops and their information input lines.
Simplified flip-flop function

tables. Q denotes the current
state and Q+ denotes the
resulting state as a
consequence of the information
inputs and the control signal.
(a) SRflip-f!op. {b) Oflip-flop.

(c) JKflip-flop. (d) Tflip-flop.
Flip-flop next-state tables. Q denotes the current state. and Q+ denotes

the resulting state as a consequence of the information inputs and
the control signal.

a) SR Flip Flop
Step 1: Derive the Next State table Step 2: K-Map to derive
characteristic equation
b) JK Flip Flop
Step 1: Derive the Next State table Step 2: K-Map to derive
characteristic equation
c) D Flip Flop
Q+ =D
d) T Flip Flop

REGISTERS
A register is simply a collection of flip-flops taken as an entity. The basic
function of a register is to hold information within a digital system so as to
make it available to the logic elements during the computing process.
A flip-flop can store 1-bit information. So an n-bit register has a group of n flip-
flops and is capable of storing any binary information/number containing n-bits.
Since a register consists of a finite number of flip-flops and since each flip-flop
is capable of storing a 0 or a 1 symbol, there are only a finite number of 0-1
combinations that can be stored in a register. Each of these combinations is
known as the state or content of the register.
Registers that are capable of moving information position wise upon the
occurrence of a clock signal are called shift registers. These registers are
normally classified by whether they can move the information in one or two
directions, i.e., unidirectional or bidirectional.
The manner in which information is entered into and outputted from a register is
another way in which they are categorized. There are two basic ways in which
these transfers are done: serially or in parallel.
When information is transferred in a parallel manner, all the 0-1 symbols that
comprise the information are handled simultaneously as an entity in a single
unit of time. Such information transfers require as many lines as symbols being
transferred.
On the other hand, the serial handling of information involves the symbol-by-
symbol availability of the information in a time sequence. These information
transfers only require a single line to perform the transfer.
Thus, there are four possible ways registers can transfer information: serial-in/
serial-out, serial-in/parallel-out, parallel-in/parallel-out, and parallel-in/serial-
out.
Serial-in, serial-out unidirectional shift register
Figure 6.26 illustrates the serial-in, serial-out unidirectional shift register

constructed from positive-edge-triggered D flip-flops. The Q output of each
flip-flop is connected to the D input of the flip-flop to its right.

The control inputs of all the flipflops are connected together to a common
synchronizing signal called the clock. Thus, upon the occurrence of a positive
edge of the clock signal, the content of each flip-flop is shifted one position to
the right.
The content of the leftmost flip-flop after the clock signal depends upon the
signal value on the serial-data-in line, and the content of the rightmost flip-flop
prior to the clock signal is lost. The output from the shift register occurs at the
rightmost flip-flop on the serial-data-out line.
For the register of Fig: 6.26, if the initial content of the four flip-flops is 1011
and a logic-0 is applied to the serial-data-in line prior to the positive edge of the
clock signal, then the content of the register becomes 0101 after the positive
edge of the clock signal. The signal value that is shifted in, i.e., the logic-0,
becomes available as an output on the serial-data-out line after four clock
pulses.
In some applications, the information within a register must be preserved, but
only a reorientation of the information is desired. To achieve this, the serial-
data-out line of Fig. 6.26 is connected to the serial-data-in line.
In this way the content of the register is again shifted one position to the right
upon the occurrence of each clock signal, but the state of the leftmost· flip-flop
is replaced by the state of the rightmost flip-flop;
For example; again, assume the initial content of the register is 1011, but the
output of the rightmost flip-flop is connected to the input of the leftmost flip-
flop; Then after the occurrence of the positive edge of the clock signal, the
register contains 1101. Shift registers having this type of connection are called
circular shift registers.
Shift registers use edge triggered or pulse-triggered, i.e., master-slave, flip-
flops. Latches are not appropriate in such an application since their outputs are
subject to changes during the entire period in which they are enabled.
Serial-in, parallel-out unidirectional shift register
The serial-in, parallel-out unidirectional shift register is illustrated in Fig. In

this case, outputs are provided from each flip-flop. Once information is shifted

into the register, i.e., serial in, the information is available as a single entity, i.e.,
parallel out, at the flip-flop output terminals.
Since information is transferred into this register serially and, after an
appropriate number of shifts, made available in parallel, this type of register
provides for the serial-to-parallel conversion of information.
Parallel-in, serial-out unidirectional shift register.
The register shown in Fig. is used as a parallel-in, serial-out unidirectional

̅̅ shift
̅
register. The operation of the register is controlled by the 𝐿𝑜𝑎𝑑̅̅̅̅̅̅̅’/Shift line.
When a logic-0 signal appears on this line, the signals on the parallel-data-in
lines IAIBICID are transferred into the register upon the occurrence of a positive-
edge clock signal. ̅
Then, when a logic-1 signal appears on the 𝐿𝑜𝑎𝑑̅̅̅̅̅̅̅̅̅’/Shift line, the D flipflops
become a cascade connection that functions as a unidirectional shift register
providing the serial output. In this way, the register of Fig. provides for the
parallel-to-serial conversion of information.
By taking the outputs from the individual flip-flops, the register functions as a
parallel-in, parallel-out unidirectional shift register. It should be noted that the
register illustrated in Fig. 6.28 can also function as a serial-in, parallel-out
unidirectional shift register and as a serial-in, serial-out unidirectional shift
register.

universal shift register
The second general classification of shift registers consists of the bidirectional

shift registers. These types of registers are capable of shifting their contents
either left or right depending upon the signals present on appropriate control
input lines.
An example of a bidirectional shift register is shown in Fig. 6.29. This register
is also known as the universal shift register. Depending upon the signal values
on the select lines of the multiplexers, i.e., the mode control lines, the register
can retain its current state, shift right, shift left, or be loaded in parallel.

Each of these operations is the result of the occurrence 0f a positive edge on the
clock line. In addition, the register̅̅ is cleared asynchronously if a logic-0 is
applied to the line labeled 𝐶𝐿𝐸𝐴𝑅̅. ̅ ̅
As an illustration of the operation of the universal shift register, according to the
table in Fig. 6.29b the register performs the shift-right operation when the logic
values on the select lines S1S0 of the multiplexers are 01.
Under this condition the I1 input of each multiplexer is connected to its f output.
Thus, as seen in Fig. 6.29a, the input to the leftmost D flip-flop is the signal on
the serial-input-for-shift-right line, the input to the second leftmost D flip-flop is
the output of the leftmost D flip-flop, the input to the third leftmost D flip-flop
is the output of the second leftmost D flip-flop, and the input to the fourth
leftmost D flipflop is the output of the third leftmost D flip-flop.
Upon the occurrence of the positive-edge signal on the clock line, the register
shifts its content one position to the right. The remaining three register
operations listed in Fig. 6.29b are easily verified in a similar manner. A symbol
for the universal shift register is given in Fig. 6.29c.
COUNTERS
Counter is a sequential circuit which is used for counting pulses. Counter is the
widest application of flip-flops. It is a group of flip-flops with a clock signal
applied. Counters are of two types. Asynchronous or ripple counters and
Synchronous counters.
Depending on the way in which the counting progresses, the synchronous or
asynchronous counters are classified as follows −Up counters, Down counters
and Up/Down counters
A counter is another example of a register. Its primary function is to produce a
specified output pattern sequence. For this reason, it is also a pattern generator.
This pattern sequence might correspond to the number of occurrences of an
event or it might be used to control various portions of a digital system. In this
latter case, each pattern is associated with a distinct operation that the digital
system must perform.
As in the case of a register, each of the 0-1 combinations that are stored in the
collection of flip-flops that comprise the counter, i.e., the output pattern, is
known as a state of the counter. The total number of states is called its modulus.

Thus, if a counter has m distinct states,

then it is called a modulus-m counter
or mod-m counter for short. The order
in which the states appear is referred to
as its counting sequence.
The counting sequence is often
depicted by a directed graph called a
state diagram. Figure 6.30 shows a
state diagram for a mod-m counter
where each node, Si, denotes .one of
the states of the counter and the arrows
in the graph denote the order' in which State Diagram Counter
the states occur.
Binary Ripple Counters

Counters whose counting sequence
corresponds to that of the binary numbers are
called binary counters. The modulus of a
binary counter is 2n, where n is the number of
flip-flops in the counter. This follows from the
fact that there are 2n combinations of 0's and
1's consisting of n bits.
For the case of a binary up-counter, the
counting sequence is from 00….0(2) to
11….1(2), which is equivalent to 0(10) to (2n - 1)
(10). After reaching its maximum count, the
counting sequence is then repeated. The
counting sequence for a binary down-counter
is in reverse order, i.e., 11….1(2) to 00….0(2).
Figure 6.31a shows a four-bit binary up-
counter implemented with positive edge
triggered T flip-flops. For each positive
transition, i.e., from logic-0 to logic-1, on the
C terminal causes the flip-flop to toggle.
As this is a 4-bit up-counter, its modulus is 24=
16, its counting sequence is from 0000(2) to
1111(2). The output of the counter appears at
the Q output terminals of the four flip-flops
where the flip-flop output Qi corresponds to
the ith-order bit of the binary number.
The input to the counter is a count enable signal and a series of count pulses
applied to the flip-flop associated with the lowest-order binary digit. In this
way, as long as the count enable signal is logic-1, the Q0 flip-flop changes state
on each positive edge of a count pulse.
The control input, i.e., C, of the remaining flip-flops is connected to the 𝑄̅

output of its previous-order flip-flop. Thus, when the Qi-1 flip-flop changes,
from its 1-state to its 0-state, thereby resulting in the 𝑄̅i-1 output to change from
logic-0 to logic-1, a positive triggering edge occurs at the control input of the Qi
flipflop causing it to toggle.
Figures 6.31b-c illustrate the counter's behavior. The counter is assumed to be
initially in its 0000 state and the count enable signal is logic- 1. Upon the
occurrence of the positive edge of the first count pulse, the Q 0 flip-flop changes
to its 1-state. Since the 𝑄̅0-output terminal goes from logic-1 to logic-0, flip-flop
Q1 is not affected by the input pulse.
The state of the counter is now 0001. When the positive edge of the second
count pulse arrives, the Q0 flip-flop is again toggled. This time it returns to its 0-
state. Furthermore, since the 𝑄̅0 output goes from logic-0 to logic-1, a positive
edge appears at the control input of the Q1 flip-flop and causes it to toggle.
The change in state of the Q1 flip-flop does not affect the Q2 flip-flop since a
negative edge occurs at its control input. Hence, at the end of the second count
pulse, the state of the counter is 0010.
The third count pulse causes only the Q0 flip-flop to change state, and the count
to become 0011. When the positive edge of the fourth pulse occurs, the Q0 flip-
flop returns to its 0-state. This causes a positive edge to occur at the 𝑄̅0 terminal.
Thus, the Q1 flip-flop is toggled, returning it to its 0-state.
In addition, when the Q1 flip-flop changes its state, the Q2 flip-flop is toggled by
the logic-0 to logic-1 transition appearing at the Q1-output terminal. The counter
now stores the binary number 0100.

The binary counting sequence continues until the count 1111 is reached. At that
time, a count pulse causes the Q0 flipflop to return to its 0-state. This, in turn,
causes the Q1 flip-flop to return to its 0-state. A consequence of this change
causes the Q2 flip-flop to return to its 0-state and, finally, this change returns the
Q3 flip-flop to its 0-state.
Thus, the state of the counter becomes 0000. If any further count pulses are
applied to the counter, then it repeats its counting sequence.
This counter is known as a ripple counter since a change in state of the Qi-1 flip-
flop if used to toggle the Qi flip-flop. Thus, the effect of a count pulse must
ripple through the counter.
Ripple counters are also referred to as asynchronous counters. Recalling there
is a propagation delay between the input and output of a flip-flop, this rippling
behavior affects the overall time delay between the occurrence of a count pulse
and when the stabilized count appears at the output terminals. The worst case
occurs when the counter goes from its 11…1-state to 00…0 state since toggle
signals must propagate through the entire length of the counter.
For an n-stage binary ripple counter, the worst-case settling time becomes n x
tpd where tpd is the propagation delay time associated with each flip-flop.
Difference between asynchronous and synchronous counters:
S.NO SYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER
1. All flip flops are triggered with same Different flip flops are triggered with
clock simultaneously. different clock, not simultaneously.
2. Synchronous Counter is faster than Asynchronous Counter is slower than

asynchronous counter in operation. synchronous counter in operation.
3. Synchronous Counter does not produce Asynchronous Counter produces

any decoding errors. decoding error.
4.
Also called Parallel Counter. Also called Serial Counter.
Synchronous Counter designing as well

5. implementation are complex due to Asynchronous Counter designing as
increasing the number of states. well as implementation is very easy.
Asynchronous Counter will operate

6. Synchronous Counter will operate in any only in fixed count sequence
desired count sequence. (UP/DOWN).
7. examples are: Ring counter, Johnson examples are: Ripple UP counter,

counter. Ripple DOWN counter.
8. In synchronous counter, propagation In asynchronous counter, there is high

delay is less. propagation delay.

Synchronous Binary Counters

The settling time problem associated with ripple counters is avoided in
synchronous counters. For synchronous counters, the count pulses are applied
directly to the control inputs, C, of all the clocked flip-flops. This causes all the
flip-flops to change simultaneously after the appropriate propagation delay
associated with a single flip-flop.
Referring to the binary counting sequence
given in Fig. 6.31c, it is noted that for each
count pulse, the lowest-order flip-flop, Q0,
must toggle. Furthermore, for each of the
remaining flip-flops, a flip-flop Qi must toggle
upon the occurrence of a count pulse if all its
lower-order flip-flops, i.e., Qi-p for p = 1, 2, ... ,
i, are in their 1-states.
Figure 6.32 shows a synchronous binary up-
counter based on this observation. As is
characteristic of a synchronous counter, the
count pulses are applied to the control input,
C, of each clocked flip-flop.
Furthermore, as long as the counter is enabled,
i.e., the count-enable. signal is logic-1, the
counter follows the. binary counting sequence.
In particular, the lowest-order flip-flop, Q0,
toggles on the positive edge of each count
pulse.
The and-gate preceding each T input terminal
of the remaining flip-flops detects if all the
lower-order flip-flops are in their 1-states. If
this condition is satisfied, then the flip-flop
toggles upon the occurrence of the positive
edge of the count pulse.
Since the count pulses are applied directly to
each flip-flop, the only delay incurred between
the application of a count pulse and the
availability of the new count output is the
propagation delay time of a flip-flop.
The synchronous counter of Fig. 6.32 does
have its drawbacks. In particular, there are p
inputs to the and-gate connected to the pth
flip-flop. Thus, if the counter consists of a
large number of flip-flops, then and-gates
having a large number of inputs are required.

In addition, if there are n stages to the counter, then the output of the pth flip-flop
must appear as inputs to n-p and-gates. Again, if the number of flip-flops is
large, then the low-order flip-flops must drive a large number of gates, which
may introduce loading complications.
It is observed in Fig. 6.32 that the output of the and-gate preceding the Qi
flipflop consists of preciselythe inputs to the and-gate preceding the Qi-1 flip-
flop plus the output of the Qi- 1 flip-flop.
This observation leads to the variation of the synchronous binary counter shown
in Fig. 6.33. Now each and-gate only requires two inputs, and the output of each
flip-flop is only needed as an input to the next-stage and-gate.
In this variation, propagation delays are incurred between the positive edges of
the count pulses due to the serial connection of and-gates. This puts a constraint
on the count pulse rate. However, as typical with synchronous counters, all the
flip-flops change state simultaneously after the propagation delay time of a flip-
flop.
It should be noted in the above discussion on asynchronous and synchronous
binary counters, the counter speed was based on the availability of the next
count at the output terminals.
In this sense, synchronous counters are faster than asynchronous counters.
It is the gate delays and the flip-flop propagation delay in a synchronous counter
that determine the rate at which count pulses can be applied.
In an asynchronous counter, the allowable count pulse rate is determined by
simply the first stage of the counter. This implies that an asynchronous counter
is very fast relative to its input. That is, once the first flip-flop changes state it
can accept the next count pulse even though the change has not propagated
through the rest of the counter. However, it is not until the rippling effect is
completed that the count is available for use.
Four-bit synchronous binary counter with parallel load inputs

If provisions are made to the synchronous counter structures of Figs. 6.32 or
6.33 so that they are loaded in parallel with an initial binary number prior to the
counting operation, then the mod-2n counter can be used as a mod-m counter
where m < 2n.
The counter structure of Fig. 6.33 modified to provide for parallel loading is
shown in Fig. 6.34a.
JK flip-flops, rather than T flip-flops, are used in this network to facilitate the
handling of the parallel load inputs. Two enable signals are utilized, one is to
allow the parallel loading of the data inputs D0, D1, D2, and D3, and a second
to provide for counting.
Both of these operations are synchronized with the positive edges of the count
pulses. The load function takes precedence over the count function*.so that if a

logic-1 is placed on the load enable line, regardless of the signal value on the
count enable line; then the signal values on the data input lines, i.e., D0, D1, D2,
and D3, are entered into the four flip-flops of the counter upon the occurrence
of the positive edge of the count pulse.
If alogic-0 is applied to the load enable line and a logic-1 is applied to the count
enable line, then the network of Fig. 6.34a behaves as a binary up-counter in the
same way as the counter of Fig. 6.33.
Finally, a logic-0 applied to both the load enable and count enable lines causes
the count pulses to be ignored and the counter to retain its current state since
logic-0's appear at the J and K terminals of each flip-flop.
A symbol for the counter of Fig; 6.34a is given in Fig. 6.34b.
Figure 6.35a shows how the counter of Fig. 6.34a is converted to function as a
mod-10, i.e., decimal, counter having the counting sequence given in Fig. 6.35b.
The normal counting sequence for the counter of Fig. 6.34a is that of a 4-bit
binary up-counter when enabled with a logic-1 on the count enable input. To
limit the counting sequence to the first 10 binary numbers, an and-gate is used
to detect the count of 1001.

Starting from the 0000 state, the first occurrence of Q0 = Q3 = 1 causes the
output of the and-gate to be logic-1. Since the load function takes precedence
over the count function, by connecting the and-gate output to the load enable
input the counter is loaded with 0000, i.e., the values on the Di inputs, upon the
next occurrence of a positive edge of a count pulse. In this way, the counting
sequence is 0000, 0001, ...., 1001, 0000, etc.
Also incorporated into the counter of Fig. 6.34a is a carry output, CO, in which
a logic-1 appears whenever the counter state is 1111 and the counter is in its
count mode, i.e., when the count enable signal is logic-1 and the load enable
signal is logic-0.
This output is used for constructing

larger binary counters by cascading
two or more 4-bit binary counters.
Figure 6.36 shows the connections
necessary to construct an 8-bit binary
counter.
When the state of the upper 4-bit
binary counter is 1111, which
corresponds to the four least
significant binary digits of the 8-bit
binary counter, its carry output signal
is logic-1.
This signal is applied to the count
enable input of the lower 4-bit counter
that is used for the four most
significant binary digits of the 8-bit
binary counter.
In this way, upon the occurrence of the
positive edge of the next count pulse,
the upper 4-bit binary counter of Fig.
6.36 returns to its 0000 state, while the
lower 4-bit binary counter is
incremented by 1.


Sequential circuits:
Now, these are types and classifications of Sequential circuits.
Types of Sequential circuits:
The sequential circuits can be event driven, clock driven and pulse driven. There are two
main types of sequential circuits: (a) Synchronous and (b) Asynchronous.
 (a). Asynchronous Sequential circuits –
Asynchronous circuits do not synchronize with positive edge or negative edge of the
clock signal, that means, the outputs of asynchronous sequential circuits do not
change or affect at the same time and change their state immediately when there is a
change in the input signal. So, these circuits are faster and independent of the internal
clock pulses. But these circuits have uncertainty in the outputs and are difficult to
design.
 (b). Synchronous Sequential circuits –

Synchronous circuits synchronize with either positive edge or negative edge of the
clock signal, that means, the outputs of synchronous sequential circuits change or
affect at the same time. These circuits use clock signal and level input (or pulsed with
restrictions on pulse width and circuit propagation). Since they wait for the next clock
pulse to arrive to perform the next operation, so these circuits are a bit slower
compared to asynchronous. Level output changes state at the start of an input pulse
and remains in that until the next input or clock pulse. The synchronous sequential
circuit can be locked or unlocked (or pulsed).

Flip-Flops and Its Applications: Module - 3

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Digital System Design (18EC34)

Module 3/RNSIT/ECE Page 1

Fig.3.1 Combinational Circuit

Drawbacks of Combinational circuits:

Fig.3.2 Sequential Circuit

Difference between Characteristics of Combinational and Sequential circuits

Module 3/RNSIT/ECE Page 2

S.NO. COMBINATIONAL CIRCUITS SEQUENTIAL CIRCUITS

handle. than combinational circuits.

Clock signals are required and it is

Elementary building blocks are logic

These circuits are slower than

3.1 Basic Bistable element:

Fig.3.3 Basic Bistable Element

The working of the bistable element

Module 3/RNSIT/ECE Page 3

 When Q=1, it is Set state. [Normal output]

Difference between Flip-flop and Latch

3 It is an edge triggered device. It is a level triggered device.

Gates like NOR, NOT, AND, NAND are

They are classified into asynchronous or There is no such classification in

It forms the building blocks of many Can be used to design sequential

Module 3/RNSIT/ECE Page 4

3.2.1 The SR Latch (Set- Reset Latch)

Fig 3.4 (c)

Module 3/RNSIT/ECE Page 5

3.2.2 The 𝑺̅ 𝑅̅ Latch

Module 3/RNSIT/ECE Page 6

Fig 3.8 (c)

3.2.3 An Application of the SR Latch: A Switch Debouncer

Module 3/RNSIT/ECE Page 7

Module 3/RNSIT/ECE Page 8

Module 3/RNSIT/ECE Page 9

The Gated D Latch

Q='0' , Clk='0' and D='x' :-

S' = Clk (nand) S

Q='0' , Clk='1' and D='0/1' :-

S' = Clk (nand) S

Module 3/RNSIT/ECE Page 10

3.3 TIMING CONSIDERATIONS

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Propagation delays from high-low, low-high assumed equal.

3.3.2 Minimum Pulse Width

3.3.3 Setup and Hold Times

Module 3/RNSIT/ECE Page 13

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When J=0, K=1

When J=1, K=0

Module 3/RNSIT/ECE Page 15

condition. This undesirable behavior can be eliminated by Edge triggering of JK flip-flop

Module 3/RNSIT/ECE Page 16

3.4 MASTER-SLAVE FLIP-FLOPS (PULSE-TRIGGERED FLIP-FLOPS)

In addition to latches, there are two other general categories of flip-flops.

Module 3/RNSIT/ECE Page 17

The Master-Slave SR Flip-Flop

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The behavior of the master-slave SR flip-flop is summarized by the function

Module 3/RNSIT/ECE Page 20

The Master-Slave JK Flip-Flop

S-R Clocked Flip-Flop

Module 3/RNSIT/ECE Page 21