Lab Report 3

Digital System Design Lab

Name: Asghar Ismail

18-CP-01

Section: Alpha

Department: Computer Engineering

Submitted To: Sir Naveed Baloch

Due Date: 12th April 2021

 Lab Tasks:

Question no 1: Design an Arithmetic Logical Unit with two 8-bit

inputs and one 8-bit output. Include 32 operations, Opcode should
be 5-bit.

Solution:

CODE: Test Bench :

module ALU( module ALU_tb ;

input [7:0] A,B, // ALU 8-bit Inputs
input [4:0] ALU_Sel,// ALU wire CarryOut ;
Selection
wire [7:0] ALU_Out ;
output [7:0] ALU_Out, // ALU 8-bit
Output reg [3:0] ALU_Sel ;
output CarryOut // Carry Out Flag reg [7:0] A ;
); reg [7:0] B ;
reg [7:0] ALU_Result; integer i;
wire [8:0] tmp; ALU
assign ALU_Out = ALU_Result; // ALU DUT (
out .CarryOut (CarryOut ) ,
assign tmp = {1'b0,A} + {1'b0,B}; .ALU_Out (ALU_Out ) ,
assign CarryOut = tmp[8]; // Carryout .ALU_Sel (ALU_Sel ) ,
flag .A (A ) ,
always @(*) .B (B ) );
begin
initial
case(ALU_Sel)
5'b00000: // Addition begin
ALU_Result = A + B ; #10 ALU_Sel = 5'b00000;
5'b00001: // Subtraction A = 8'd5; B = 8'd7;
ALU_Result = A - B ;
5'b00010: // Multiplication for (i=0;i<=15;i=i+1)
ALU_Result = A * B; begin
5'b00011: // Division ALU_Sel = ALU_Sel + 8'h01;
ALU_Result = A/B; #10;
5'b00100: // Logical shift left end
ALU_Result = A<<1;
5'b00101: // Logical shift right end
ALU_Result = A>>1;
endmodule
5'b00110: // Rotate left
ALU_Result = {A[6:0],A[7]};
5'b00111: // Rotate right
ALU_Result = {A[0],A[7:1]};
5'b01000: // Logical and
ALU_Result = A & B;
5'b01001: // Logical or
ALU_Result = A | B;
 5'b01010: // Logical xor
ALU_Result = A ^ B;
5'b01011: // Logical nor
ALU_Result = ~(A | B);
5'b01100: // Logical nand
ALU_Result = ~(A & B);
5'b01101: // Logical xnor
ALU_Result = ~(A ^ B);
5'b01110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
5'b01111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
5'b10000: // Lesser comparison
ALU_Result = (A<B)?8'd1:8'd0 ;
5'b10001: // Increment A
ALU_Result = A + 1'b1;
5'b10010: // Decrement A
ALU_Result = A - 1'b1;
5'b10011: // Increment B
ALU_Result = B + 1'b1;
5'b10100: // Decrement B
ALU_Result = B - 1'b1;
default: ALU_Result = A + B ;
endcase
end
endmodule

Output:
Question no 2: Design a register file, consisting of 32, 8-bit
registers, include RW 1-bit signal to differentiate between the
operations.

CODE : Test Bench:

module Register_File(RF_out, RF_Din, module Register_File_tb ;

RF_Add,RF_RW);
input [7:0] RF_Din; reg RF_RW ;
input [4:0] RF_Add; reg [4:0] RF_Add ;
input RF_RW; reg [7:0] RF_Din ;
output [7:0] RF_out; wire [7:0] RF_out ;
reg [7:0] RF_out; Register_File
reg [7:0]RF[31:0]; DUT ( .RF_RW (RF_RW ) ,
always@( RF_Din or RF_Add or RF_RW) .RF_Add (RF_Add ) , .RF_Din (RF_Din ) ,
if(RF_RW ==0) .RF_out (RF_out ) );
RF_out <= RF[RF_Add]; initial
else begin
RF[RF_Add]<= RF_Din;
endmodule RF_RW = 1'b1; RF_Din = 8'b00000001;
RF_Add = 5'b00000;

#2 RF_Din = 8'b00000010;
RF_Add = 5'b00001;

#2 RF_Din = 8'b00000011;
RF_Add = 5'b00010;

#2 RF_Din = 8'b00000100;
RF_Add = 5'b00011;

#2 RF_RW = 1'b0;
RF_Add = 5'b00000;

#2 RF_RW = 1'b0;
RF_Add = 5'b00000;

#2 RF_Add = 5'b00001;

#2 RF_Add = 5'b00010;

#2 RF_Add = 5'b00011;

end
endmodule
Output:

Question no 3: Integrate the above two tasks to make a complete

data-path.

Solution :
CODE: Test Bench:

module Project (RF_OUT ,A , B , module Register_File_tb ;

ALU_Sel,MUX_SEL,RF_ADD,RF_W,OUT_
Module); reg RF_RW ;
reg [4:0] RF_Add ;
output [7:0] RF_OUT; reg [7:0] RF_Din ;
input [7:0] A , B ,OUT_Module; wire [7:0] RF_out ;
input [4:0] ALU_Sel,RF_ADD; Register_File
input MUX_SEL,RF_W; DUT (
.RF_RW (RF_RW ) ,
wire [7:0] ALU_OUT,MUX_OUT; .RF_Add (RF_Add ) ,
.RF_Dmodule Register_File_tb ;

ALU ALU1 (.A(A) reg RF_RW ;

,.B(B),.ALU_Sel(ALU_Sel), reg [4:0] RF_Add ;
.ALU_Out(ALU_OUT)); reg [7:0] RF_Din ;
wire [7:0] RF_out ;
MUX_2X1 mux Register_File
(.MUX_OUT(MUX_OUT),.MUX_IN1(ALU_ DUT (
OUT),.MUX_IN2(OUT_Module),.MUX_SEL( .RF_RW (RF_RW ) ,
MUX_SEL)) ; .RF_Add (RF_Add ) ,
.RF_Din (RF_Din ) ,
Register_File .RF_out (RF_out ) );
regFile1(.RF_out(RF_OUT) initial
,.RF_Add(RF_ADD),.RF_RW(RF_W),.RF_Di begin
n(MUX_OUT));
RF_RW = 1'b1;
RF_Din = 8'b00000001;
RF_Add = 5'b00000;
endmodule
#2

RF_Din = 8'b00000010;
RF_Add = 5'b00001;

#2

RF_Din = 8'b00000011;
RF_Add = 5'b00010;

#2

RF_Din = 8'b00000100;
RF_Add = 5'b00011;

#2

RF_RW = 1'b0;
 RF_Add = 5'b00000;

#2

RF_RW = 1'b0;
RF_Add = 5'b00000;

#2

RF_Add = 5'b00001;

#2

RF_Add = 5'b00010;

#2

RF_Add = 5'b00011;

end
endmodule
in (RF_Din ) ,
.RF_out (RF_out ) );
initial
begin

RF_RW = 1'b1;
RF_Din = 8'b00000001;
RF_Add = 5'b00000;

#2

RF_Din = 8'b00000010;
RF_Add = 5'b00001;

#2

RF_Din = 8'b00000011;
RF_Add = 5'b00010;

#2

RF_Din = 8'b00000100;
RF_Add = 5'b00011;

#2
 RF_RW = 1'b0;
RF_Add = 5'b00000;

#2

RF_RW = 1'b0;
RF_Add = 5'b00000;

#2

RF_Add = 5'b00001;

#2

RF_Add = 5'b00010;

#2

RF_Add = 5'b00011;

end
endmodule

Output: