library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity multiplicador4 is
port ( A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
P: out STD_LOGIC_VECTOR (7 downto 0));
end multiplicador4;
architecture Behavioral of multiplicador4 is
-- Declaración del componente Sumador Completo
component sumcompl
port ( A: in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
Cout: out STD_LOGIC;
S: out STD_LOGIC);
end component;
-- Declaración intermedia
signal AB0,AB1,AB2,AB3: STD_LOGIC_VECTOR (7 downto 0);
signal C1 : STD_LOGIC_VECTOR (1 downto 0);
signal P1: STD_LOGIC_VECTOR (1 downto 0);
begin
-- Multiplier input
AB0(0) <= A(0) and B(0); -- Primera fila del producto
AB0(0) <= A(1) and B(0);
AB1(0) <= A(0) and B(1); -- Segunda fila del producto
AB1(1) <= A(1) and B(1);

AB2(0) <= A(0) and B(0); -- Primera fila del producto

AB2(0) <= A(1) and B(0);
AB3(0) <= A(0) and B(1); -- Segunda fila del producto
AB3(1) <= A(1) and B(1);

-- Port Mapping Full Adder 8 times and Half Adder 4 times

FA1: sumcompl port map(AB0(1), AB1(0), '0', C1(0), P1(0));
FA2: sumcompl port map(AB1(1), '0', C1(0), C1(1), P1(1));
FA3: sumcompl port map(AB2(1), AB3(0), '0', C1(0), P1(0));
FA4: sumcompl port map(AB3(1), '0', C1(0), C1(1), P1(1));
-- Mulitplier output
P(0)<= AB0(0);
P(1)<= P1(0);
P(2)<= P1(1);
P(3)<= C1(1);
end Behavioral;