EJEMPLO CON PROCEDURE

ARCHIVO DE TESTBENCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder4_tb is
-- Port ( );
end adder4_tb;

architecture Behavioral of adder4_tb is

component adder4
port(a,b:in std_logic_vector(3 downto 0);
cin:in std_logic;
sum:out std_logic_vector(3 downto 0);
Cout:out std_logic);
end component;

-- entradas
signal a,b:std_logic_vector(3 downto 0):="0000";
signal cin:std_logic:='0';
 EJEMPLO CON PROCEDURE
-- salidas
signal sum:std_logic_vector(3 downto 0);
signal Cout:std_logic;

begin

UUT:adder4 port map(a=>a,b=>b,Cin=>Cin,sum=>sum,Cout=>Cout);

process
begin
wait for 10 ns;
cin<='0';
a<="0101";
b<="1010";
wait for 10 ns;
cin<='0';
a<="0001";
b<="0011";
wait for 10 ns;
cin<='1';
a<="0000";
b<="1111";
end process;

end Behavioral;