Rapport 2 :VHDL

Réalisé par : RAIS Aya

LAZREK Ghita

Additionneur 4 bits
library ieee;
use ieee.std_logic_1164.all;
entity add_simple is
port (a,b,cin:in std_logic;s,cout:out std_logic );
end add_simple;
architecture add_s of add_simple is
begin
s<=a xor b xor cin;
cout <= (a and b) or ((a xor b) and cin );
end add_s;
transcodeur bcd

SIGNAL c: std_logic_vector (3 downto 0);

SIGNAL nb: std_logic_vector (3 downto 0);

begin

nb<= not(b)+1;

u1:additionneur_1bit PORT MAP (a(0),nb(0),'0',r(0),c(0));

u2:additionneur_1bit PORT MAP (a(1),nb(1),'0',r(1),c(1));

u3:additionneur_1bit PORT MAP (a(2),nb(2),'0',r(2),c(2));

u4:additionneur_1bit PORT MAP (a(3),nb(3),'0',r(3),c(3));

n<='1' when b>a else

'0';

end arch_sous_4 bits;

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY soustr_4bits IS
PORT(
a,b: IN std_logic_ vector(3 downto 0 );
r: OUT std_logic_ vector(3 downto 0 );
n: OUT std_logic);
END ENTITY;
architecture arch_sous_4 bits of soustr_4 bits IS
COMPONENT additionneur_1bit IS
PORT(
a,b,cin:IN std_logic;
sum,cout:OUT std_logic);
END COMPONENT ;
Mux 4 vers 1
library ieee;
use ieee.std_logic_1164.all;
entity muxbb is
end muxbb;
architecture muxb of muxbb is
signal za,zb,zc,zs:bit ;
component mux1
port(A,B,C: in bit ; S: out bit);
end component ;
begin
inst: mux1 port map(za, zb,zc,zs);
process
 begin
za<='0'; zb<='0';zc<='0' ;wait for 10
ns;
za<='0'; zb<='1';zc<='0' ;wait for 10
ns;
za<='1'; zb<='0';zc<='0' ;wait for 10
ns;
za<='1'; zb<='1';zc<='0' ;wait for 10
ns;
za<='0'; zb<='0';zc<='1' ;wait for 10
ns;
za<='0'; zb<='1';zc<='1' ;wait for 10
ns;
za<='1'; zb<='0';zc<='1' ;wait for 10
ns;
za<='1'; zb<='1';zc<='1' ;wait for 10
ns;
wait;
end process;
end muxb;
comparateur 4 bits
library ieee;
use ieee.std_logic_1164.all;

entity comparateur is
port (A,B:in std_logic_vector(3 downto
0 );egale,sup,inf:out std_logic);
end comparateur;
architecture architect of comparateur is
begin
egale <='1' when A=B else '0';
inf <='1' when A<B else '0';
sup <='1' when A>B else '0';
end architect ;
compteur arduino 16
Registre à décalage d'un bit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity regist_decal_1bit is
port(horloge,entree : in std_logic;
sortie: out std_logic_vector(7 downto 0));
end regist_decal_1bit;

architecture arch_regist_decal_1bit of
regist_decal_1bit is
signal data : std_logic_vector(7 downto
0):="11110000";
begin
process(horloge)
begin
if horloge='0' then
data <= entree& data(7 downto 1);
end if;
end process;
 process(data)
begin
sortie<=data;
end process;
end arch_regist_decal_1bit;
soustracteur 4 bits
Réalisation d'une bascule JK
library ieee;
use ieee.std_logic_1164.all;
entity bas_jk is
port (J,K,H:in std_logic;
S:out std_logic );
end bas_jk;
architecture comp_bascule_jk of bas_jk is
signal mise:std_logic:='1';
begin
process(H,J,K)
 begin
if (H='1') then
if (J='0' and K='0') then mise<=mise;
elsif (J='0' and K='1') then mise<='0' ;
elsif (J='1' and K='0') then mise<='1';
else mise<= not mise ;
end if;
end if;
end process ;
S<=mise;
end comp_bascule_jk;