Design of Arithmetic Calculator Using Fpga

DESIGN OF ARITHMETIC CALCULATOR USING FPGA
CHAPTER - 1
SCOPE OF THE PROJECT
1. The aim of the project is to learn the fundamentals of FPGAs and implement an
arithmetic calculator on an FPGA board. The following objectives were envisaged to
achieve the aim of the project :-
1.1. To understand the functioning of Field Programmable Gate Arrays.
1.2. To learn and use the Very High Speed Hardware Description [VHDL] Language.
1.3. To implement an arithmetic calculator on a commercial FPGA board.
2. The project has been implemented in VHDL on an Actel ProAsic3 evaluation

board. The IDE used for programming VHDL codes is Libero 8.4.
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CHAPTER - 2
INTRODUCTION
2.1. Introduction to the Project
2.1.1. The aim of the project is to design and implement few arithmetic operations
namely addition, subtraction, multiplication of two numbers and square root, square and
cube of any number using FPGA where VHDL is used to program it. Any two numbers
are given through the DIP switches as input and the operations are assigned to the 6 keys
of the 2*3 matrix. On pressing the keys respective operation is performed and the output
is displayed through LEDs of the output DIP switches.
2.1.2. The Figure 2.1. gives a brief idea of the project.
DIP SWITCHES
I/P =P DIPSWITCHES
O/P=Q
DIP SWITCHES
I/P =R
FPGA CHIP
LCD DISPLAY
KEY BD
Fig. 2.1.
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2.1.3. The FPGA used here is ACTEL ProAsic 3 and is configured from the source
computer using a parallel port cable. The code is created using VHDL in LiberoIDE 8.4
version software supported by Actel. The code thus created is checked for errors and
burnt on to the FPGA chip and the functionality of the code is then checked. Fig. 2.2
shows the process involved in creating a code and burning it into the FPGA.
Fig. 2.2.
2.1.4. The required 9v power supply for the board has been given through an Adaptor.
2.1.5. The codes are burnt into the FPGA through a parallel port cable.
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CHAPTER - 3
BACKGROUND
3.1. Introduction to Programmable Logic Devices
3.1.1 Programmable Logic Devices are devices with a configurable logic. In simple
words it means that they can be programmed to behave like any digital circuit. Usually
they have flip-flops linked together with programmable interconnects. A PLD is
composed of two types of gate arrays, the „AND array‟ and the „OR array‟. These arrays
are fused together by the program, depending on the user‟s requirements. In PLD, the
software decides how to connects the groups of transistors (gates) or the groups of gates
(macro cells) in a particular way. Two of the most popular PLDs are CPLDs and FPGAs.
3.1.2 CPLD or Complex Programmable Logic Device is an erasable programmable

logic device that can be programmed with a schematic or a behavioral design. CPLD are
based on EPROM or EEPROM technology. It is composed of AND gate arrays and is
surrounded by the interconnect area. CPLD logic gate densities range from the equivalent
of several thousand to tens of thousands of logic gates.
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Fig 3.1 CPLD Design
3.2. Introduction to FPGA
3.2.1 FPGAs are in principle derivatives of complex programmable logic devices

(CPLDs) of the early to mid 1980s. CPLDs and FPGAs include a relatively large number
of programmable logic elements. CPLD logic gate densities range from the equivalent of
several thousand to tens of thousands of logic gates, while FPGAs typically range from
tens of thousands to several million.
3.2.2 The primary differences between CPLDs and FPGAs are architectural. A CP LD
has a somewhat restrictive structure consisting of one or more programmable sum-of-
products logic arrays feeding a relatively small number of clocked registers. The result of
this is a general lack of design flexibility, with the advantage of more predictable timing
delays and a higher logic-to- interconnect ratio. FPGA architectures, on the other hand,
are dominated by interconnect. This makes them far more flexible (in terms of the range
of designs that are practical for implementation within them) but also far more complex
to design from.
3.2.3 Another notable difference between CPLDs and FPGAs is the presence in most
FPGAs of higher- level embedded functions (such as adders and multipliers) and
embedded memories. A related, important difference is that many modern FPGAs
support full or partial in-system reconfiguration, allowing their designs to be changed "on
the fly" either for system upgrades or for dynamic reconfiguration as a normal part of
system operation. This means that some FPGAs have the capability of partial re-
configuration that lets one portion of the device be re-programmed while other portions
continue running. A recent trend has been to take the coarse-grained architectural
approach a step further by combining the logic blocks and interconnects of traditional
FPGAs with embedded microprocessors and related peripherals to form complete
"systems on a programmable chip". The following figure sum it all.
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Fig 3.2 FPGA vs PLD

3.3. Basic FPGA Architecture
3.3.1 The typical basic architecture consists of an array of logic blocks and routing
channels. Multiple I/O pads may fit into the height of one row or the width of one
column. Generally, all the routing channels have the same width (number of wires).
Fig 3.3 Basic FPGA Architecture
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3.3.2 The typical FPGA logic block called “Configurable Logic Blocks” or CLBs
consists of a 4- input lookup table (LUT), and a flip- flop, as shown. There is only one
Fig 3.4 Logic block

output, which can be either the registered or the unregistered LUT output. The logic
block has four inputs for the LUT and a clock input. Since clock signals are normally
routed via special-purpose dedicated routing networks, they are accounted for separately
from other signals.
3.3.3 For this architecture, the locations of the FPGA logic block pins are shown below.
Fig 3.5 Logic Block Pin Locations
Each input is accessible from one side of the logic block, while the output pin can
connect to routing wires in both the channel to the right and the channel below the logic
block. Each logic block output pin can connect to any of the wiring segments in the
channels adjacent to it. This is more clear from the figure below.
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Fig 3.6 Logic block pin to routing channel interconnect
3.3.4 Generally, the FPGA routing is un segmented. That is, each wiring segment spans
only one logic block before it terminates in a switch box. As shown in Fig 3.7. By turning
on some of the programmable switches within a switch box, longer paths can be
constructed. [2]
Fig 3.7 Unsegmented FPGA routing
3.3.5 Whenever a vertical and a horizontal channel intersect there is a switch box. In
this architecture, when a wire enters a switch box, there are three programmable switches
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that allow it to connect to three other wires in adjacent channel segments. The pattern, or
topology, of switches used in this architecture is the planar or domain-based switch box
topology (Fig 3.8.). In this switch box topology, a wire in track number one connects
only to wires in track number one in adjacent channel segments, wires in track number 2
connect only to other wires in track number 2 and so on. The figure below shows the
connections in a switch box.
Fig 3.8 Switch box topology
3.3.6 Modern FPGA families expand upon the above capabilities to include higher level
functionality fixed into the silicon. Having all these common function embedded into the
silicon reduces the area required and gives those functions increased speed.
3.4. Memory
3.4.1 While the first FPGAs didn't have internal memories, all new FPGAs have
internal memories. That increases a lot their scope of applications.
There are many parameters affecting RAM operation. The main parameter is the number
of processes that can access the RAM simultaneously.
"single-port" RAMs: only one process can read/write the RAM.
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"dual-port" or "quad-port" RAMs: 2 or 4 processes can read/write.

To find out how many processes are available, we can count the number of separate
address buses going to the RAM. Each process has a dedicated address bus. Each process
has also either a read, a write, or both data buses. Writing to the RAM is usually done
synchronously. Reading is usually also done synchronously but can also sometimes be
done asynchronously. RAM blocks are usually dedicated memory block ("block rams").
Xilinx the largest and most popular manufacturer of FPGA has a lot of flexibility in the
RAM distribution, because it also allows using the logic-cells (a logic-cell is composed of
a small lookup table, some gates and a D-flip- flop, each logic-cell then can be connected
to other logic-cells through wires placed around the logic-cells) as tiny RAMs
("distributed RAM"). Altera, another manufacturer usually takes another approach and
builds different-size block rams around the device.
3.5. User Pins
3.5.1 FPGA pins fall into 2 categories: "dedicated pins" and "user pins".
About 20% to 30% of the pins of an FPGA are "dedicated pins", which means that they
are hard-coded to a specific function. The rest are user pins. The dedicated pins fall into
the 3 following sub-categories.
(a) Power pins. Might be ground pins (GND) or power pins (core or I/O pins).
(b) Configuration pins. These pins are used to "download" the FPGA.
(c) Dedicated inputs, or clock pins. These pins are able to drive large and wide nets
inside the FPGA, suitable for clocks or signals with large output points
.
3.5.2 The bulk of the pins of an FPGA are "user pins" (called "I/Os"). I/O stands for
"input-output". They have following characteristics:-
(a) User have total control over user I/O pins. They can be programmed to be inputs,
outputs, or bi-directional
(b) Each "I/O pin" is connected to an "I/O cell" inside the FPGA. The "I/O cells" are
powered by the VCCIO pins (IO power pins).
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3.6. Powe r Supply Requirements
3.6.1 FPGAs usually require 2 voltages to operate: a "Core voltage" and an "IO
voltage". Each voltage is provided through separate power pins.
(a) The internal core voltage (called VCCINT ), is used to power the logic gates and
flip- flops inside the FPGA. The voltage can range from 5V for older FPGA
generations, to 3.3V, 2.5V, 1.8V, 1.5V and even lower for the latest devices. The
core voltage is fixed (set by the model of FPGA ).
(b) The I/O voltage (called VCCIO) is used to power the I/O blocks of the FPGA.
3.7. Introduction To HDL

HDL (Hardware Description Language) is a software language, which is used to
describe hardware for the purpose of Simulation, Modeling, Testing, Design and
Documentation of Digital systems. There are mainly two types of HDL
(a) VHDL (Very High Speed Integrated Circuit HDL)
(b) Verilog
3.8. VHDL
3.8.1. VHDL is a language which is permanently extended and revised. The original
standard itself needed more than 16 years from the initial concept to the final, official
IEEE standard. When the document passed the committee it was agreed that the s tandard
should be revised every 5 years. The first revision phase resulted in the updated standard
of the year 1993. Independently of this revision agreement, additional effort is made to
standardize "extensions" of the pure language reference. These extensions cover for
examples packages (std_logic_1164, numeric_bit, numeric_std) containing widely
needed data types and subprograms, or the definition of special VHDL subsets like the
synthesis subset IEEE 1076.6.[1]
3.8.2. The latest extension is the addition of analogue description mechanisms to the
standard which results in a VHDL superset called VHDL-AMS.VHDL is used mainly for
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the development of Application Specific Integrated Cicuits (ASICs). Tools for the
automatic transformation of VHDL code into a gate-level netlist were developed already
at an early point of time. This transformation is called synthesis and is an integral part of
current design flows. For the use with Field Programmable Gate Arrays (FPGAs) several
problems exist. In the first step, boolean equations are derived from the VHDL
description, no matter, whether an ASIC or a FPGA is the target technology. But now,
this boolean code has to be partitioned into the configurable logic blocks (CLB) of the
FPGA. This is more difficult than the mapping onto an ASIC library. Another big
problem is the routing of the CLBs as the available resources for interconnections are the
bottleneck of current FPGAs.
3.8.3. While synthesis tools cope pretty well with complex designs, they obtain usually
only suboptimal results. Therefore, VHDL is hardly used for the design of low
complexity Programmable Logic Devices (PLDs). VHDL can be applied to model system
behaviour independently from the target technology. This is either useful to provide
standard solutions, e.g. for micro controllers, error correction (de-)coders, etc, or
behavioural models of microprocessors and RAM devices are used to simulate a new
device in its target environment.
3.8.4. The design process always starts with a specification phase: The component
which is to be designed is defined with respect to function, size, interfaces, etc. Despite
the complexity of the final product, mainly simple methods, based on paper and pencil
most of the time, are being used. After that, self-contained modules have to be defined on
the system level. Their interaction is described very precisely and interfaces (inputs,
outputs, data formats), clock speed and reset mechanism are specified. With that
information at hand, pure simulation models of the circuit can be developed. Behaviour
models of standard components can be integrated into the system from libraries of
commercial model developers. The overall system can already be simulated.[2]
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3.8.5. On the logic level, the models that have to be designed are described with all the
synthesis aspects in view. As long as only a certain subset of VHDL constructs is used,
commercial synthesis programs can derive the boolean functions from this abstract model
description and map them to the elements of an ASIC gate librar y or the configurable
logic blocks of FPGAs. The result is a netlist of the circuit or of the module on the gate
level. Finally, the circuit layout for a specific ASIC technology can be created by means
of other tools from the netlist description. Every transition to a lower abstraction level
must be proven by functional validation signals for the simulation) the module's
responses are compared. VHDL is suitable for the design phases from system level to
gate level. [5]
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CHAPTER - 4
IMPLEMENTATION DETAILS
4.1. Introduction to ProASIC3 Evaluation Board

The ProASIC 3 Evaluation board is a kit developed for the beginners who are
interested in designing simple circuits and implement their functionality on this kit. The
FPGA used here is ProASIC 3 and has 250,000 gates. The code for designing any circuit
can be written using Hardware Description Languages. The languages generally used are
Very High Speed Hardware Description language (VHDL) and Verilog. The software
using which the codes are created is Libero IDE 8.4 version.
4.2. Specifications of the Pro ASIC3 Evaluation Board

The ProASIC3 Evaluation Board consists of the following:
· Polarity free power supply connector that accepts 9 VDC (standard power supply is
provided with kit)
· On-board power supplies and their indicators (5.0 V / 3.3 V / 2.5 V / 1.5 V)
· 32 bidirectional inputs/outputs (used to apply input or get output from the device)
· On-board 40 MHz oscillator and an optional oscillator socket for user expansion
· 16 × 2 alphanumeric LCD to facilitate detailed messages from the FPGA
· A keyboard with 6 keys in 2 × 3 matrix format
· Power-on reset circuit with reset key
· Two serial port interfaces for UART/serial code verification
· 10-pin lockable FlashPro3 connector for programming the device through a FlashPro3
programmer
· 25-pin parallel port connector with standard cable for programming the device through a
parallel port, as when an on-board
JTAG interface is implemented
· Jumpers for selection of programmer (FlashPro3/parallel port) and programming
voltage
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· Jumpers to select 1.5 V / 2.5 V / 3.3 V I/O voltage on bank-0 / bank-1 / bank-2 / bank-3
· Test points for voltage / clock and reset.
4.3. Introduction to Libero IDE 8.4

This software was built with the aim of creating codes for the Actel FPGAs. The
first version was Libero IDE 8.0. The latest version available is Libero IDE 8.4. For using
this software the company provides a license without which installation of this software
is impossible. The License comes in different packages. We are using Libero Gold Node
Lock free license package which has validity for 1 year.
4.4. Installation of Libero IDE 8.4

To install this software the company provides a license. The license can be
downloaded from the Actel‟s website. The procedure for downloading the license is as
follows:
(a) Enter into Actel‟s website www.actel.com.
(b) Click the Download option.
(c) A window opens, in which an option for License download is shown.
(d) On clicking the License option, a screen appears asking for username and
password. Without which downloading the license is not possible.
(e) New users have to create a new ID.
(f) After creating the ID go ahead with procuring the license.
(g) Every license is procured on the Volume ID of the hard disk of the computer
Used to create the code. An example of a Volume ID is shown below,
“0245-0AB4”
(h) Enter the volume ID.
(j) The license will be sent to the personnel‟s mail ID.
(k) The license file comes in license.dat format. Save the file in a folder named
flexlm inside the C drive.
(l) Right click on the My Computer icon on the desktop and click properties.
(m) A window showing the System properties is opened. Click the Advanced option
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inside the window.

(n) The Advanced window opens. Click the Environment Variables button which
will open a new window.
(p) Click the New button of the User Variable for Administrator sub window. A
Window for New User Variable opens. Enter LM_LICENSE_FILE in the Variable
Name field and C:\flexlm\license.dat in the Variable Value field. Click OK.
(q) Click the New button of the User Variable for Administrator sub window once
Again. A window for New User Variable opens. Enter SYNPLIFY_FILE in the
Variable Name field and C:\flexlm\license.dat in the Variable Value field. Click OK.
(r) Load the Libero IDE 8.4 disc and install the software.
(s) The installation of the software is complete.
4.5. Design Flow

The steps involved in the Design flow are as follows:
Step 1 – Creating a New Project
Step 2 – Perform Pre-Synthesis Simulation
Step 3 – Synthesize the Design in Synplify
Step 4 – Perform Post-Synthesis Simulation
Step 5 – Implement the Design with Designer
Step 6 – Perform Timing Simulation with Back-Annotated Timing
Step 7 – Generate the Programming File
4.5.1. Creating a Ne w Project

This step uses the Libero IDE HDL Editor to enter an Actel VHDL design.
(a) Double-click the Libero IDE icon on desktop to start the program.
(b) From the File menu, select New Project. This displays the New Project Wizard as
shown in Fig 4.5.1. [4]
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.
Fig 4.5.1.
(c) Enter Project name.
(d) Select HDL type.
(e) Select project Family, Die, and Package.
(f) Select ProASIC3, the A3P250 die and 208 PQFP for the package as shown in Fig
4.5.2.
Fig 4.5.2
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g) Click Next to select Integrated Tools in the New Project Wizard as shown in Fig 4.5.3.
Fig 4.5.3.
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(h) Click the Restore Defaults button to use the default tools included with Libero IDE.
(j) Click next to add project files as shown in Fig 4.5.4.
Fig 4.5.4.
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(k) Click next to finish the new project wizard as shown in Fig 4.5.5.
Fig 4.5.5
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4.6. Adding HDL to the Project

(a) From the file menu, click new and select the VHDL Entity, Enter Simple Calculator
in the name field and Click OK as shown in Fig 4.6.1.
Fig 4.6.1.
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(b) Enter the VHDL file and clicks save. The design file counter appears in the Design
Hierarchy as shown in Fig 4.6.2.
Fig 4.6.2.
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(c) Check the HDL in the file by right clicking simple calculator.vhd and select Check
HDL file. This check for any errors in the HDL file as in Fig 4.6.3.
Fig 4.6.3.
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4.7. Synthesize the design in Synplify

(a). EDIF netlist for the design using Synplify is generated by double-click the Synplify
Synthesis in the Libero IDE process window as shown in Fig 4.7.1..
Fig 4.7.1.
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(b). Synthesis process using Synplify is completed as checked for any errors and
warnings as shown in Fig 4.7.2. and Fig 4.7.3.
Fig 4.7.2.
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Fig 4.7.3.
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4.8. Implementing the Design with Designer

(a) After creating and testing, the design is implemented using the Actel designer
Software.
(b) Click Designer Place and Route in the Libero IDE Design flow window as shown in
Fig 4.8.1.
Fig 4.8.1.
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(c) Assign a pin number to all of the signals as shown in Fig 4.8.2.
Fig 4.8.2.
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(d) Compilation and layout of Design in the designer is carried out as shown in Fig
4.8.3.
Fig 4.8.3.
(e) Timing Simulation with Back – Annotated Timing is done in the Designer.
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(f) Click on the Programming file to generate programming file as shown in Fig 4.8.4.
Fig 4.8.4.
4.9. Programming the Device

4.9.1. From the project manager window select the Programming icon. The window
appears as in Fig 4.9.1.
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Fig 4.9.1.
4.9.2. The window in Fig 4.9.2. shows the FlashPro programming window. If the power
supply is not connected to the kit and the programming is continued then the programmer
status in this window shows “SCAN CHAIN FAILED”.
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Fig 4.9.2.
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4.9.3. When the program is burnt onto the FPGA, first it erases the previous program
stored in it and then does the programming and verification of the STAPL file loaded on
to the kit. Fig 4.9.3. and Fig 4.9.4. shows the Erasing and Programming windows
respectively.
Fig 4.9.3.
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Fig 4.9.4.
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4.9.4. Once the program is loaded successfully then the Program Status shows “RUN
PASSED” as shown in Fig 4.9.5.
Fig 4.9.5.
4.10. Design of Full Adder and its code
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladd IS
PORT(Cin, A, B:IN STD_LOGIC;
S, Cout :OUT STD_LOGIC);
END fulladd;
ARCHITECTURE LogicFunc OF fulladd IS

BEGIN
S <= A XOR B XOR Cin;
Cout<=(A AND B) OR (Cin AND A) OR (Cin AND B);
END LogicFunc;
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4.11. Design of Square Root and its code
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;
entity Sm is -- subtractor multiplexor

port ( x : in std_logic;
y : in std_logic;
b : in std_logic;
u : in std_logic;
d : out std_logic;
bo : out std_logic);
end Sm;
architecture circuits of Sm is
signal t011, t111, t010, t001, t100, td : std_logic;
begin -- circuits of Sm
t011 <= (not x) and y and b;
t111 <= x and y and b;
t010 <= (not x) and y and (not b);
t001 <= (not x) and (not y) and b;
t100 <= x and (not y) and (not b);
bo <= t011 or t111 or t010 or t001;
td <= t100 or t001 or t010 or t111;
d <= td when u='1' else x;
end architecture circuits; -- of Sm
architecture circuits of arithopern is
signal zer : std_logic := '0';
signal one : std_logic := '1';
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signal x00, x01, x02, x03, x04, x05, u_0 : std_logic;

signal b00, b01, b02, b03, b04, b05 : std_logic;
signal x12, x13, x14, x15, x16, u_1 : std_logic;
signal b12, b13, b14, b15, b16 : std_logic;
signal x24, x25, x26, x27, u_2 : std_logic;
signal b24, b25, b26, b27 : std_logic;
signal x36, x37, u_3 : std_logic;
signal b36, b37 : std_logic;
signal divide_clk : std_logic_vector (23 downto 0);
signal kbd_clk : std_logic;
signal qclk :std_logic;
begin -- circuits of psqrt
-- x y b u d bo
s36: entity work.Sm port map(P(6), one, zer, u_3, x36, b36);
s37: entity work.Sm port map(P(7), zer, b36, u_3, x37, b37);
s26: entity work.Sm port map(x36 , u_3, b25, u_2, x26, b26);
s27: entity work.Sm port map(x37 , zer, b26, zer, x27, b27);
s00: entity work.Sm port map(P(0), one, zer, zer, x00, b00);
s01: entity work.Sm port map(P(1), zer, b00, zer, x01, b01);
s02: entity work.Sm port map(x12 , u_1, b01, zer, x02, b02);
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u_0 <= not b05;
u_1 <= not b16;
u_2 <= not b27;
u_3 <= not b37;
end architecture circuits;
4.12.Integrated Code
-- Calculator.vhd
library ieee;
entity Sm is -- subtractor multiplexor

port ( x : in std_logic;
y : in std_logic;
b : in std_logic;
u : in std_logic;
d : out std_logic;
bo : out std_logic);
end Sm;
architecture circuits of Sm is
signal t011, t111, t010, t001, t100, td : std_logic;
begin -- circuits of Sm
t011 <= (not x) and y and b;
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t111 <= x and y and b;

t010 <= (not x) and y and (not b);
t001 <= (not x) and (not y) and b;
t100 <= x and (not y) and (not b);
bo <= t011 or t111 or t010 or t001;
td <= t100 or t001 or t010 or t111;
d <= td when u='1' else x;
end architecture circuits; -- of Sm
library ieee;
entity arithopern is -- arithematic operation

port (CLK : in std_logic; --osc clock input (40 MHz)
P : in std_logic_vector(7 downto 0);
R : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(15 downto 0);
scan_line : out std_logic_vector(1 downto 0);
key_status : in std_logic_vector(2 downto 0));
end arithopern;
architecture circuits of arithopern is

signal zer : std_logic := '0';
signal one : std_logic := '1';
signal x00, x01, x02, x03, x04, x05, u_0 : std_logic;
signal b00, b01, b02, b03, b04, b05 : std_logic;
signal x12, x13, x14, x15, x16, u_1 : std_logic;
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signal b12, b13, b14, b15, b16 : std_logic;

signal x24, x25, x26, x27, u_2 : std_logic;
signal b24, b25, b26, b27 : std_logic;
signal x36, x37, u_3 : std_logic;
signal b36, b37 : std_logic;
signal divide_clk : std_logic_vector (23 downto 0);
signal kbd_clk : std_logic;
signal qclk :std_logic;
begin -- circuits of psqrt
-- x y b u d bo
s00: entity work.Sm port map(P(0), one, zer, zer, x00, b00);
s01: entity work.Sm port map(P(1), zer, b00, zer, x01, b01);
FTP/O-149/SSC230/
u_0 <= not b05;

u_1 <= not b16;
u_2 <= not b27;
u_3 <= not b37;
--clock devider (clock i/p 40 Mhz)

process (clk,divide_clk)
begin
if clk ='1' and clk'event then
divide_clk <= divide_clk + '1' ;
end if;
end process;
kbd_clk <= divide_clk(23);

--flash counter
process (kbd_clk,scan_line)
begin
if kbd_clk ='1' and kbd_clk'event then
qclk <= qclk +1;
end if;
end process;
process (key_status,qclk,u_0,u_1,u_2,u_3,P,R)
begin
Q(15 downto 0) <= "0000000000000000";
if key_status ="011" then
Q<=P*R;
elsif key_status ="101" then
Q(7 downto 0)<= P+R;
elsif key_status ="110" then
Q(0) <= u_0;
FTP/O-149/SSC230/
Q(1) <= u_1;

Q(2) <= u_2;
Q(3) <= u_3;
end if;
end process;
end architecture circuits;
FTP/O-149/SSC230/
CHAPTER - 5
MAINTENANCE AND TROUBLE SHOOTING
5.1. Maintenance
5.1.1. The main equipment used is the Actel Proasic3 starter kit, containing the FPGA
chip and related electronics. Though it‟s been protected against over voltages and Electro
Static Discharge, care must be taken. For complete electrical characteristics datasheet
must be referred, freely available at www.actel.com
5.1.2. Electrical hygiene must be maintained while using FPGA pins for input and
output. Jumpers must be used for connecting wires to pins.
5.2. Trouble Shooting
5.2.1. The problem faced initially was in loading the license. The Libero IDE 8.4
version software can be loaded in any drive, but the license.dat file given by Actel must
be loaded only in C drive in a folder named flexlm. We loaded this folder in D drive and
a licensing error occurred. Every license is granted on the volume ID of the drive only.
The license we initially had was given on D drive Volume ID. A request for fresh license
was registered and procured on the C drives, Volume ID and loaded successfully. Any
number of licenses can be procured. The license used in this project has a validity of 1
year.
5.2.2. For proving the operations like addition, subtraction and multiplication we
initially used full adder circuit, subtractor circuit and multiplier circuits which was time
consuming and also created lot of syntax errors in the Check HDL stage in the HDL
editor. This was overcome when the fact that the libraries existed for addition, subtraction
and multiplication was revealed on detailed study of the Libero IDE 8.4 software.
FTP/O-149/SSC230/
5.2.3. Problems were faced in creating code for square root. There is no library for
square root as such. The subtractor multiplexer was used to create the square root. Lot
of syntax errors came up during the check HDL stage. Architecture circuit for Subtractor
multiplexer and for square root was created but to link them the “entity work.Sm port
map” statement was essential. We were creating the code with “entity portmap” which
generated lot of syntax errors.
5.2.4. Each operation‟s code was created individually but problem existed in integrating
them. During integration the basic mistake we committed was to operate with a
Architecture statement inside an Architecture. Architecture within an architecture is not
allowed. On removing this error the integration problem was solved.
5.2.5. Another main problem was now in assigning the operations to various keys of the
2*3 matrix. The 3 bit key_status output was fed to the FPGA chip and the operations
were assigned to each condition. Errors were generated in the “if then” statement due to
non usage of “ begin” statement which resulted in non assignment of the keys.
5.2.6. Even after the errors were cleared in the Check HDL stage, errors existed in the
synthesis stage. The Check HDL stage is only to check syntax errors, where as the
Synthesis stage also checks the mapping of the codes generated. The “key_status” was
declared as “out std_logic_vector” whereas it was supposed to be declared as “in
std_logic_vector”. This was shown as sythesis error in Synplify stage.
5.2.7. The Synplify stage also generated warnings showing generation of latches at
output port “Q”. Latches are generated if the output is not assigned any initial value
within the process statement. Then “Q” was assigned “0000000000000000” and the
warning was overcome.
5.2.8. On configuring the FPGA with the created programming file it was found that the
program status window showed “SCAN CHAIN FAILED”. On DIDR it was found that
FTP/O-149/SSC230/
the parallel port cable, 9V adaptor and a IC was faulty. The adaptor was giving 12V
instead of 9V and the cable lacked continuity. On replacing all three of them the problem
was solved.
FTP/O-149/SSC230/
CHAPTER - 6
FINANCIAL IMPLICATION
All the components were procured from the Actel ProAsic3 FPGA manufacturers.
The cost of procurement and the repair cost during the course of the project are
mentioned below:-
Actel ProAsic3 Starter Kit - Rs. 8000/-

Repair of the kit - Rs. 1700/-
Parallel Port Cable - Rs. 450/-
9V Adaptor - Rs. 500/-
Total Cost of Project - Rs.10,650/-
FTP/O-149/SSC230/
CHAPTER - 7
CONCLUSION
7.1. Codes for addition, multiplication, subtraction of any two numbers and square
root, square and cube of any number were created
7.2. The codes were integrated and successfully burnt into the FPGA.
7.3. The operations namely, addition, multiplication and square root were assigned to
the 3 keys of the 2*3 key matrix. Problems arose in assigning the rest three operations.
FTP/O-149/SSC230/
CHAPTER - 8
FUTURE WORK
8.1. Future Work
8.1 This project is the first step towards performing designs based on DSP
applications. Projects like Implementation of UART Transmitter and Receiver, 10 base
T Ethernet, FM Receiver etc., can also be taken into with the help of this project. This
gives a platform from where complex VHDL statements can also be tried. The code used
in this project doesn‟t involve any component creation. Codes using component creation
can also be made with this idea.
8.2 With the characteristics of FPGA any stimulation of any device can be connected
to network and parameters be controlled from remote locations. To quote a few examples
FPGA can be configured for FM Modulation/Demodulation. Serial and parallel
communication between local devices can also be taken into if the ports are used
effectively.
FTP/O-149/SSC230/
CHAPTER - 9
BIBLIOGRAPHIES
Following materials were referred to complete this project:

[1] J Bhasker, VHDL Primer, Prentice Hall of India, 3rd edition.
[2] Wayne Wolf, FPGA-Based System Design, Pearson Education, Inc, 2004
edition
[3] Douglas Perry, VHDL, Tata McGraw Hill, 3 rd edition
[4] Actel starter manual
[5] Various Online VHDL Tutorials
FTP/O-149/SSC230/
APPENDIX
I. Features of Actel ProAsic 3 FPGA
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology

• 130-nm, 7- Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live At Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM (FROM)
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)
In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except A3P030) via JTAG (IEEE1532-compliant)

• FlashLock® to Secure FPGA Contents
FTP/O-149/SSC230/
Low Powe r
• 1.5 V Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/ 2.5 V/
1.8 V/1.5 V, 3.3 V PCI/3.3 V PCI-X (except A3P030), and
LVCMOS 2.5 V/5.0 V Input
• Differential I/O Standards: LVPECL and LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os (A3P030 only)
• Programmable Output Slew Rate (except A3P030) and
Drive Strength
• Weak Pull- Up/Down
• IEEE1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL (except
A3P030)
• Six CCC Blocks, One with an Integrated PLL
FTP/O-149/SSC230/
• Flexible Phase-Shift, Multiply/Divide, and Delay Capabilities

• Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs (except A3P030)
• Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
• True Dual-Port SRAM (except x18)
• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz
• Soft Core Support in ARM7-Ready Devices
ProAsic3 Product Family as shown in Table 1
Table 1
FTP/O-149/SSC230/
II. 208-PIN PQFP
FTP/O-149/SSC230/
III. Pin Configuration
FTP/O-149/SSC230/
FTP/O-149/SSC230/

Design of Arithmetic Calculator Using Fpga

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Design of Arithmetic Calculator Using Fpga

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DESIGN OF ARITHMETIC CALCULATOR USING FPGA

SCOPE OF THE PROJECT

2. The project has been implemented in VHDL on an Actel ProAsic3 evaluation

2.1. Introduction to the Project

2.1.2. The Figure 2.1. gives a brief idea of the project.

3.1. Introduction to Programmable Logic Devices

3.1.2 CPLD or Complex Programmable Logic Device is an erasable programmable

Fig 3.1 CPLD Design

3.2. Introduction to FPGA

3.2.1 FPGAs are in principle derivatives of complex programmable logic devices

Fig 3.2 FPGA vs PLD

Fig 3.3 Basic FPGA Architecture

Fig 3.4 Logic block

Fig 3.5 Logic Block Pin Locations

Fig 3.6 Logic block pin to routing channel interconnect

Fig 3.7 Unsegmented FPGA routing

Fig 3.8 Switch box topology

"dual-port" or "quad-port" RAMs: 2 or 4 processes can read/write.

3.5. User Pins

3.6. Powe r Supply Requirements

3.7. Introduction To HDL

4.1. Introduction to ProASIC3 Evaluation Board

4.2. Specifications of the Pro ASIC3 Evaluation Board

4.3. Introduction to Libero IDE 8.4

4.4. Installation of Libero IDE 8.4

inside the window.

4.5. Design Flow

4.5.1. Creating a Ne w Project

4.6. Adding HDL to the Project

4.7. Synthesize the design in Synplify

4.8. Implementing the Design with Designer

4.9. Programming the Device

4.10. Design of Full Adder and its code

ARCHITECTURE LogicFunc OF fulladd IS

4.11. Design of Square Root and its code

entity Sm is -- subtractor multiplexor

signal x00, x01, x02, x03, x04, x05, u_0 : std_logic;

entity Sm is -- subtractor multiplexor

t111 <= x and y and b;

entity arithopern is -- arithematic operation

architecture circuits of arithopern is

signal b12, b13, b14, b15, b16 : std_logic;

u_0 <= not b05;

--clock devider (clock i/p 40 Mhz)

kbd_clk <= divide_clk(23);

Q(1) <= u_1;

MAINTENANCE AND TROUBLE SHOOTING

5.2. Trouble Shooting

Actel ProAsic3 Starter Kit - Rs. 8000/-

Total Cost of Project - Rs.10,650/-

8.1. Future Work

Following materials were referred to complete this project:

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

Standard (AES) Decryption (except A3P030) via JTAG (IEEE1532-compliant)

High-Performance Routing Hierarchy

• Flexible Phase-Shift, Multiply/Divide, and Delay Capabilities

II. 208-PIN PQFP

III. Pin Configuration

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